Question about STM32 EXTI

icdiy · ‎2013-12-16

Posted on December 17, 2013 at 06:46

Hi Sir,

I'd like to ask one question about STM32 EXIT.

If interrupt pin asserted during EXT_IMR is disabled, will the interrupt be recorded by EXTI_PR and intrrupt is issued to CPU core immediately after EXT_IMR re-enabled? Thanks.

icdiy · ‎2013-12-17

Posted on December 18, 2013 at 08:23

Help me please...Thanks

chen · ‎2013-12-18

Posted on December 18, 2013 at 10:41

Have you read the data sheet?

In general, once the NVIC/EXTI is configured and enabled, IRQs will be 'registered'.

If the IRQ are masked, it is registered until serviced or cleared.

If the IRQ is not masked, the ISR will be executed.

If a higher priority IRQ triggers - it will interrupt the current context (ISR or normal execution).

''

If interrupt pin asserted during EXT_IMR is disabled, will the interrupt be recorded by EXTI_PR and intrrupt is issued to CPU core immediately after EXT_IMR re-enabled?

''

If an IRQ is masked and it triggers, then it is 'registered' in the EXTI_PR ( FYI you can manually clear it ).

Once the IRQ is unmasked, if it is still 'registered' in the EXTI_PR it will cause the CPU to execute the ISR for that IRQ.

Answer - YES

I suggest you try it.

icdiy · ‎2013-12-18

Posted on December 19, 2013 at 01:34

Thanks for your kind reply.

In my case, only EXTI_IMR is disabled, IMR of the CPU core is not masked.

And I set the rising edge trigger for the external interrupt pin.

External interrupt pin goes high during EXTI_IMR is disabled.

I hope that this interrupt can be recorded in EXTI_PR and CPU will be interrupted after EXTI_IMR is re-enabled. But unfortunately, the experiment result is not that.

This really make me confused.

chen · ‎2013-12-19

Posted on December 19, 2013 at 10:11

Hi

Did you read the manual - the whole section on Interrupts and Events?

OK, I may have misled you.

I re-read the section and I have now come to this conclusion :

''A pending register maintains the status line of the interrupt

requests.''

The EXTI_PR register maintains which IRQs are pending.

If the IRQ is masked - then it cannot be triggered and therefore it cannot be pending.

I did say to try it out for yourself - now you know.

chen · ‎2013-12-19

Posted on December 19, 2013 at 10:45

Hi

I just had further thoughts :

''In my case, only EXTI_IMR is disabled, IMR''

Did you disable the EXTI or did you mask it?

There is a big difference.

If you disable an IRQ - it can never trigger. If you mask it - it can trigger but the CPU has been set to ignore it.

Enable is done in the EXTI part of the IRQ controller.

Masking is done in the NVIC part of the IRQ controller.

Assuming you want to register the EXTI IRQ but not trigger the ISR and

If the masking really does stop the IRQ from being registered, then another way

to do what you want is to set the IRQ priority level and then change the IRQ priority mask. This allows the CPU to stop responding to IRQs below a certain level.

The ST manual refers to the ARM manual - you will have to go and download it from the ARM web site.

Please Read the manuals and then read it again.

Even I have problem understanding what they are going on about!

icdiy · ‎2013-12-19

Posted on December 20, 2013 at 00:10

Thank you sir:)

I know there is two parts for the interrupt: EXTI and NVIC

NVIC is part of the ARM core, I did nothing to control the NVIC in my experiment, so interrupt is always enabled in NVIC.

What I did is to write EXTI_IMR register to mask one external interrupt.

I hope the external interrupt happens during EXTI_IMR is masked can be recorded by EXTI_PR, then after EXTI_IMR is re-enabled EXTI will send this recorded interrupt request to NVIC . But the result is not as I expected.

icdiy · ‎2013-12-19

Posted on December 20, 2013 at 00:34

Hi Sir,

I read both the Coretex-M3 doc and the STM32 reference manual.

In Figure 20 of the STM32 reference manual,

we can see the interrupt output to NVIC is (EXTI_IMR & EXTI_PR).

And EXTI_IMR is only used here. It will not affect the edge detect logic, neither it will affect the pending request register.

So I think even EXTI_IMR is masked(write EXTI_IMR as 0), the external interrupt request can be detected and recorded in EXTI_PR, so the corresponding bit in EXTI_PR will be set as 1. But no interrupt will be issued to CPU core because EXTI_IMR is 0. But the interrupt will be generated as soon as EXTI_IMR is re-enabled(write EXTI_IMR as 1).

But the experiment result is that interrupt happens during EXTI_IMR is 0 will just be ignored. So I really am confused about this.

icdiy · ‎2013-12-19

Posted on December 20, 2013 at 00:44

I read both the Cortex-M3 doc and the STM32 reference maunal.

In Figure 20 of the STM32 reference manual, we can see the interrupt request from the EXTI controller to the CPU core is (EXTI_IMR & EXTI_PR).

EXTI_IMR is only used here. Neither the edge detection logic and the pending request register is affected by EXTI_IMR

So in my understanding, if external interrupt happens during EXTI_IMR is maksed(write as 0), it still can be detected and recorded in EXTI_PR. No interrupt will be generated to CPU core beause EXTI_IMR is 0. And once EXTI_IMR is re-enabled(write as 1), the interrput request will be generated to CPU core.

But the experiment result is that the external interrupt happens during EXTI_IMR is masked will just be ignored.

I am really confused about this.

From: sung.chen_chung

Posted: Thursday, December 19, 2013 10:45 AM

Subject: Question about STM32 EXTI

Hi

I just had further thoughts :

''In my case, only EXTI_IMR is disabled, IMR''

Did you disable the EXTI or did you mask it?

There is a big difference.

If you disable an IRQ - it can never trigger. If you mask it - it can trigger but the CPU has been set to ignore it.

Enable is done in the EXTI part of the IRQ controller.

Masking is done in the NVIC part of the IRQ controller.

Assuming you want to register the EXTI IRQ but not trigger the ISR and

If the masking really does stop the IRQ from being registered, then another way

to do what you want is to set the IRQ priority level and then change the IRQ priority mask. This allows the CPU to stop responding to IRQs below a certain level.

The ST manual refers to the ARM manual - you will have to go and download it from the ARM web site.

Please Read the manuals and then read it again.

Even I have problem understanding what they are going on about!

chen · ‎2013-12-20

Posted on December 20, 2013 at 11:10

Hi

That is good work finding out the correct path and behavior in the documentation.

Be careful - carefully re-read the descriptions and make sure that your interpretation of the document is the same.

I often have to re-read (often many times) to make sure I have understood the behaviour as documented.

These things are just so complicated!

Saying that - it is possible you have found a problem.

There is one other document to look at :

Errata

All CPU producers end up making mistakes and the CPU does not do what it is suppose to. They produce a document (called errata) to tell you what does not work, in which revision of the CPU and sometimes how to overcome the problem. You need to download the errata for the processor that you are using.