QUADSPI, hammered by FTF interrupts as soon as I set CR?

[Chris Rice]

Hello, so I am creating a QUADSPI driver to interface with some external FLASH, and what I've discovered is that as soon as I set my QUADSPI_CR register, I am spammed by FIFO threshold interrupt (FTF) interrupts. I guess this makes sense, because my CCR register is not set yet, so my FMODE is zero, which is indirect write, and the interrupt is telling me that there are free spots in the FIFO and I can write to them now.

However, I'm not actually ready to make a transfer yet, I have no data to write yet, I'm just initializing my unit. Per RM0394 page 351, "triggering the start of a command", I would not expect any action to start until I've written to CCR, AR, or DR.

So apparently I misunderstand the intended sequence of things. I can't clear the FTF interrupt, and I don't have data to write yet. I am using DMA, should I not enable the FTF interrupt at all? Should I not set CR.EN until I am ready to transfer?

Below is my initialization code (GPIO, clock, and DMA set up not shown), and my FTF interrupts start firing right away, hanging my program, and even though I'm not ready to send data. What should I be doing differently?

Thanks very much.

//////////////////////////////////////////////////////////////////////////
// Set QUADSPI CR [RM0394, 15.5.1]
//////////////////////////////////////////////////////////////////////////
 
QUADSPI->CR = 0x64170305;  // = 01100100000101110000001100000101
 
//    0:0    EN         = 1         = 0x1   QUADSPI is enabled
//    1:1    ABORT      = 0         = 0x0   No abort requested
//    2:2    DMAEN      = 1         = 0x1   DMA is enabled for indirect mode
//   3:3    TCEN       = 0         = 0x0   Timeout counter disabled in memory mapped (FMODE=11)
// 4:4    SSHIFT     = 0         = 0x0   No sample shift
// 6:6    DFM        = 0         = 0x0   Dual Flash mode disabled
// 7:7    FSEL       = 0         = 0x0   FLASH 1 selected in single flash mode (DFM=0)
//11:8   FTHRES     = 0011      = 0x3   FTF is set if there are FTHRES+1 or more [free bytes available to be written] or [loaded bytes that can be read] in the FIFO
// 16:16  TEIE       = 1         = 0x1   Transfer error interrupt (TEI) enabled
// 17:17  TCIE       = 1         = 0x1   Transfer complete interrupt (TCI) enabled
/ /18:18  FTIE       = 1         = 0x1   FIFO Threshold interrupt (FTI) enabled
// 19:19  SMIE       = 0         = 0x0   Status match interrupt (SMI) disabled
// 20:20  TOIE       = 1         = 0x1   Timeout interrupt (TOI) enabled
// 22:22  APMS       = 0         = 0x0   Automatic polling mode (FMODE=10) stopped only by abort or disable
 //    23:23  PMM        = 0         = 0x0   AND match mode for automatic polling mode (FMODE=10)
 //      31:24  PRESCALER  = 01100100  = 0x64  Pre-scaler for QuadsPI CLK based on AHB clock; [QuadSPI CLK]=AHB/[PRESCALER+1]
                                    
//////////////////////////////////////////////////
// enable the QUADSPI IRQ
// This is IRQ=71, so it is the bit 7 of the second register (ISER[1])
//////////////////////////////////////////////////
                
NVIC->ISER[2] = (0x1 << 7);
 
               QUADSPI->DCR =
                    (27) << QUADSPI_DCR_FSIZE_Pos
                    | 1 << QUADSPI_DCR_CSHT_Pos // nCS stays high for 2 cycles
                    | 0 << QUADSPI_DCR_CKMODE_Pos // CLK idles at low state
                    ;