PVD enable latency - SOLVED

[lpc921]

Posted on March 08, 2016 at 01:47

I am using the STM32L053 MCU on the Nucleo board. The MCU is powered by 1.8V during the test. If I add some delay after turnning on the PVD, then the PVDO bit returns 1, with no delay it returns 0.

I could not find how long it takes for the PVDO bit to become valid in the datasheet. Has anyone tested that? Here is the initialise routine:

void
PVD_Config(
void
)
{
/*##-1- Enable Power Clock #################################################*/
__PWR_CLK_ENABLE();
/* Wait for internal VREF ready */
while
( 0 == __HAL_PWR_GET_FLAG( PWR_FLAG_VREFINTRDY ) );
/*##-2- Configure the NVIC for PVD #########################################*/
HAL_NVIC_SetPriority(PVD_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(PVD_IRQn);
sConfigPVD.PVDLevel = PVD_THRESHOLD_1V9;
sConfigPVD.Mode = PWR_MODE_IT_RISING_FALLING;
HAL_PWR_PVDConfig(&sConfigPVD);
/* Enable the PVD */
HAL_PWR_EnablePVD();
/* Add some delay here */
if
( 0 == __HAL_PWR_GET_FLAG( PWR_FLAG_PVDO ) )
{
/* Do something */
}
}

[Walid FTITI_O]

Posted on March 10, 2016 at 11:18

Hi liu.bill.003,

I think the behaviour that you see  is related to your voltage supply satatus. The PVD is working, and the PVDO flag is switching between 1 and 0 to indicate a change in VDD level comparing to the programmable voltage threshold.

As mentioned about PVDO, in STM32L0 reference manual below

:

Bit 2

PVDO:

PVD output

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.

0: V

DD

is higher than the PVD threshold selected with the PLS[2:0] bits.

1: V

DD

is lower than the PVD threshold selected with the PLS[2:0] bits.

Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after

Standby or reset until the PVDE b

i

t is set.

-Hannibal-

[lpc921]

Posted on March 15, 2016 at 00:53

Hi Hannibal,

Thanks for your reply. Today I solved my problem. The flag I am polling for Vrefint_ready is wrong. The correct bit is SYSCFG_CFGR3_VREFINT_RDYF. No delay is required after enabling PVD. The corrected polling code is pasted below.

/* Wait for internal VREF ready */
__SYSCFG_CLK_ENABLE();
while
( 0 == __HAL_SYSCFG_GET_FLAG( SYSCFG_FLAG_VREF_READY ) );

[Walid FTITI_O]

Posted on March 15, 2016 at 10:58

Hi liu.bill.003, 

It's good that you have find the right way to your need. Thanks for your contribution.-Hannibal-