Posted on May 17, 2011 at 14:19 /* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
I think that should read PCLK1 = HCLK / 2
Isn't the max clock for APB1 36 MHz, the timers taking an HCLK (APB1 * 2) feed so can get to 72 MHz (AHB), but none of the other peripherals are rated up there.
