cancel
Showing results for 
Search instead for 
Did you mean: 

L1 cache for stm32H743

Franzi.Edo
Senior
Posted on November 20, 2017 at 20:53

Dear all,

I am trying to set-up a new board using an stm32H743.

In my tests, I initialized the MPU in order to use the cache L1 with the Flash.

When I initialize the MPU to use the cache, the results are really impressive (about 1.8 faster than without L1).

Unfortunately, the system is not stable; I often have 'hardfault' situation.

Any suggestion of how to use L1 with the internal Flash?

Here is my initialization code before activating the cache.

Best regards

  Edo

 ...

// New attributes for the FLASH area (0x08000000)

// Change the attribute only in the executable area

   MPU->CTRL = 0x00000000;    // Disable the MPU

   MPU->RNR  = 0x00000000;    // Region 0

   MPU->RBAR = 0x08000000 | (1<<4) | (0<<0); // Address, valid & region 0

   MPU->RASR = (0<<28)    // Instruction fetches enabled

            | (6<<24)     // Unprivileged read-only

            | (0<<19)     // TEX: 000 Memory attribute

            | (1<<18)     // S: 0

            | (1<<17)     // C: 1

            | (0<<16)     // B: 0 un-sharable, Normal, outer and inner write-through,

                          //      no write allocate

            | (0<<8)      // Corresponding sub-region is enabled

            | (20<<1)     // 2-MB

            | (1<<0);     // Region enable

  MPU->CTRL = (1<<2)      // Enable the usage of all the default map

             | (1<<1)     // MPU is enabled during the fault

             | (1<<0);    // MPU enabled

   MEMO_SYNC_BARRIER;

   DATA_SYNC_BARRIER;

   INST_SYNC_BARRIER;

   ...

#stm32h7
1 ACCEPTED SOLUTION

Accepted Solutions
Franzi.Edo
Senior
Posted on November 20, 2017 at 23:42

Solved! It seems necessary to initialize the MPU segment for the RAM area used by the system (in my case the RAM of 512-KBytes). I don't know yet why, but it works. Without this initialization the RAM is not reliable and the system crashes.

Best regards

  Edo

View solution in original post

4 REPLIES 4
Franzi.Edo
Senior
Posted on November 20, 2017 at 23:42

Solved! It seems necessary to initialize the MPU segment for the RAM area used by the system (in my case the RAM of 512-KBytes). I don't know yet why, but it works. Without this initialization the RAM is not reliable and the system crashes.

Best regards

  Edo

Posted on November 21, 2017 at 22:39

Hi Edo,

Why did you have to enable MPU in-order to enable L1 cache? Cant't L1 data/instruction cache be enabled while the MPU is disabled?

Thanks,

Evgeny

Posted on November 21, 2017 at 23:09

In Cortex-M7, it's the MPU which governs the cache. Read AN4839 .

JW

Posted on November 22, 2017 at 20:06

Hi Evgeny and Waclawek,

The answer of 

Waclawek is correct. MPU is necessary to define the L1 characteristics: ie. memory location and size as well as the access specifications (i.e. cashable, write-through, etc).

Best regards

Edo