I need to process samples from two different ADCs by transferring their samples to the FMAC via DMA. This is done by writing repeat values to FMAC->WDATA. Both ADCs have the same trigger and I want to insure one ADC's value arrives before the other. I know I can adjust the priority, but they are both using channels on DMA1 and they trigger at the exact same time, so I’m still suspicious there might be more to it. Is priority enough?
To gain confidence, you can arrange the ADC inputs to have very distinct values, and use the DMA to transfer their values to GPIOs, observed by oscilloscope/LA.
Right...that's only confidence though. I'm going to be adding more and more DMA channels and traffic, it could get really hard to test if the order isn't consistent, hence the the search of definitive info.
