Intermittently switching a PWM/ONESHOT timer output to high impedance

[John Craven]

Posted on April 03, 2018 at 16:05

I have read a few short posts around this forum, that suggest disabling a timer in PWM/OC mode, will change the output pins to high impedance.

As background, I am trying to interface with a device that requires a PWM control pulse 500-2500us width as an input signal at 50-100Hz, The device replies with telemetry, on the same line, by creating a brief 1us wide pulse on the same line. The timing between the end of the control input pulse and the brief telem pulse determines the telem value (0.5ms equals zero and 5.5ms is fullscale). There is a cycle of 11 telem values. The cycle start is marked, by the device not sending a telem pulse, followed by 11 replies. 

Device interface spec, includes that i must yield the line (high impedance) after generating the control pulse and use a 2k pullup on my end for my 3.3V logic.

I would like to send the control input pulse using a ONESHOT mode timer that is triggered based on another timer that is not relevant to this discussion.

If i disable the ONESHOT timer at the end of its pulse (end of pulse callback), will its output go high impedance? I have a scheme, based on another input capture timer to measure the telem value timing and on its input capture callback, can i simply re-enable the ONESHOT timer and have it ready for the next trigger event?

I am looking for confirmation from somebody who has done something similar or can confirm that temporarily disabling a timer changes it output to high impedance and simple re enable will reverse that and timer will function on next event.

If disabling the timer, does not set out to High impedance, i am open to suggestions. Obviously, i can add external components, tristate buffer/driver, but i am looking for soft solution before adding hardware.

[waclawek.jan]

Posted on April 03, 2018 at 16:21

It's not the *timer* you are going to enable/disable, but the *channel*, using its respective TIMx_CCER.CCyE bit. The timer itself remains to run and react etc., so when reenabling you may perhaps want to reset TIMx_CR1.CEN and TIMx_CNT too.

There are other ways to skin the cat, of course, e.g. changing AF to Input in GPIO, or changing timer mode from output compare to input capture in TIMx_CCMR. More options are available in the Advanced Timers (TIM1, TIM8), see TIMx_BDTR and TIMx_CR2; but you probably don't want to go that far.

JW

[John Craven]

Posted on April 03, 2018 at 16:43

Thank you Jan.

I can try disabling the channel instead.

I was going to use a retriggerable one pulse mode mode timer for the outgoing control pulse.

The channel won't get disabled until the pulse finish callback.

Correct me if i am wrong, but i think the timer CNT is reverent until the next trigger.

The CNT stops at ARR when the pulse completes and stays there until the next trigger. I have solid control of the upstream trigger.

The channel should be re-enabled long before the  next trigger occurs.

If i was using PWM, then i agree, i probably would have to massage other things like the CNT.

[waclawek.jan]

Posted on April 03, 2018 at 16:47

The channel should be re-enabled long before the  next trigger occurs.

Then it's just the simple matter of TIMx_CCER.CCyE.

JW

[waclawek.jan]

Posted on April 03, 2018 at 16:51

You may want to have a look at Output control bits for complementary OCx and OCxN channels with break feature table in the TIM1/TIM8 chapter. It applies to non-advanced timers too, taking into account the missing TIMx_BDTR bits (i.e. only the 1st and 3rd line of the table applies) and missing OCxN outputs.

JW

[John Craven]

Posted on April 03, 2018 at 17:12

Yes i found that table in one of the Ref Manuals while i was searching high impedance and 'Hi-Z'

However, i decided to see if guy like you had a simple solution before trying to digest the 'break feature'.

Ill try the channel disable later today.

If it doesn't work we can go down that other rabbit hole! LOL

[John Craven]

Posted on April 05, 2018 at 21:18

Update: Disable/Enable of the channel worked.

However, going a bit further, the scheme is really a lot like I2C and I needed to use open-drain on the timer output with external pullup (about 2k for 3.3V logic).

Master pulls line low for period proportion to control signal.

Then device pulls line (pulse) after a delay. The delay between master control pulse and the brief device pulse is a telem value.

Anyways i got it working.

As an experiment, i removed the channel disable/enable code.

The master-device scheme share the line and it still works. Control is good and i am decoding the telem.

So my master timer output (with open drain) is effectively HI-Z, when not outputting a pulse.

Anyways, i learned a couple new tricks. Thanks for your help Jan.