IIS3DWB High-Rate FIFO/DMA Data Transfer on STEVAL-STWINBX1

[Taha]

Hi all,

I’m working on a project using the STEVAL-STWINBX1, and my main goal is to use the IIS3DWB vibration sensor as a high-speed vibrometer. I’m still pretty new to embedded programming (about 2 months in), so please bear with me!

Project setup so far:

• Board: STEVAL-STWINBX1 (STM32U585AI MCU)

• Using: Only the IIS3DWB vibration sensor (not the other sensors for now)

• Peripherals: SPI2 (for IIS3DWB), UART2 (for debug/streaming), FreeRTOS

• Goal: Read high-frequency vibration data, and eventually store it for later analysis

What I’ve tried:

• I set up IIS3DWB via SPI2 and am running it at the full 26.7 kHz ODR (output data rate).

• Because the data rate is so high, using an interrupt for every data-ready signal floods the CPU.

• To handle this, I enabled the IIS3DWB internal FIFO (3KB, ~200 samples), set a watermark/threshold, and use the FIFO threshold interrupt to trigger reading.

• My ISR releases a semaphore, which a FreeRTOS task then picks up to read out the FIFO using:

  iis3dwb_fifo_out_multi_raw_get(&dev_ctx, fifo_data, num);

• After that, I try to send the samples out via UART (just for testing), and I have another task blinking an LED to check if the CPU is getting starved.

The problem:

• If I try to send all the FIFO data out via UART (using HAL UART transmit, not DMA), the FIFO quickly overflows and I lose data.

• It seems UART can’t keep up with the sensor, and the rest of the system starts missing interrupts/tasks.

• (Side question: Does iis3dwb_fifo_out_multi_raw_get automatically clear the read data from FIFO, or do I need to manually manage FIFO pointers or clear it after reading?)

What I want to try next:

• Move all heavy data movement (sensor-to-memory, memory-to-UART) to DMA, so the CPU can handle higher-level logic and avoid being starved.

• My idea is:

  1. FIFO threshold interrupt fires → notifies a FreeRTOS task.

  2. The task reads data out of the FIFO into a buffer (possibly with DMA, if supported).

  3. Another task (or maybe same) sends the buffer out via UART using DMA as well.

• I’m not 100% sure about the best way to architect this. My main goal is to reliably stream or store high-frequency sensor data without losing samples or overwhelming the CPU.

Questions:

1. What’s the best practice for moving high-rate sensor data from the IIS3DWB FIFO to UART or storage on this hardware?

2. Any gotchas with the DMA setup for SPI/IIS3DWB and UART on the STM32U5 series? Are there sample projects or HAL/LL code snippets for this?

3. For those with experience: Do I need to “clear” the FIFO manually after reading, or does the read function automatically pop the entries? (Can’t find this clearly in the docs.)

4. Any advice for task/interrupt/DMA priorities to make sure nothing is missed, especially as a beginner to FreeRTOS and STM32 DMA?

5. If you have working code, a block diagram, or even just advice on the pipeline, I’d really appreciate it!

I’m just a student, so I’m still learning a lot of the STM32 and sensor stack. If you spot any flaws in my thinking or have a more robust architecture, please let me know! Open to all suggestions, links, or example code.

My repository is: https://github.com/YumTaha/STWINBX1/tree/FIFO-Tasks
I track my learning there so I can always have it if I want to implement functions together

another thing I ran into is all the examples and help out there is mostly for other sensors rather than IIS3DWB, I couldn't find anything about this sensor.

Thanks so much!