I2S Channel Side Flag Issue
Options
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2016-04-14 7:31 AM
Posted on April 14, 2016 at 16:31
Hello ,
I have configured I2S3ext of STM32F4 which is interfaced with audio codec. In our environment , Sample Frequency is @ 8 KHz . CHSIDE bit of I2S status register always remains in reset state . I have checked no overrun flag has not been set . What could be the other reason for not setting this CHSIDE bit ?- Pinkesh
#i2s-channel-side-issue
Labels:
- Labels:
-
I2S
This discussion is locked. Please start a new topic to ask your question.
2 REPLIES 2
Options
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2016-04-14 8:27 AM
Posted on April 14, 2016 at 17:27
> I have configured I2S3ext
Transmitter or receiver? Which mode? Post perhaps the I2S3ext registers' content. Which pins are you using for I2S3/ext? JWOptions
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2016-04-14 11:20 PM
Posted on April 15, 2016 at 08:20
Hi Jan,
In our environment , PC11 - I2S3ext _SD line PC12 - I2S3_SD line PC10 - I2S3_CK PA15 - I2S3_WS line I2S3 as full duplex in which I2Sext configured as Slave receiver & I2S as Slave Transmitter while external device work as I2S master . After configuring I2S, SPI3 Peripheral contents are CR2 - 0x80 SR - 0x02 I2SCFGR - 0xC00 I2S3ext Peripheral Contents are CR2 - 0x40 SR - 0x02 I2SCFGR - 0xD00 - Pinkesh