2020-02-22 08:56 AM
I want declare a uint32_t variable which will be updated/written by one of the cores and read by another core. Any sample code (or document) available for Arm Cortex-M4 and Cortex-M7 cores?
2020-02-22 09:46 AM
You'd need it to both be volatile, and actively manage write buffers and cache coherency.
Look at the HSEM examples for inter-core comms.
STM32Cube_FW_H7_V1.5.0\Projects\STM32H747I-EVAL\Examples\HSEM\HSEM_ResourceSharing
2020-02-23 07:48 AM
Thanks for details.
HSEM_ResourceSharing is example for resource (GPIO in this case) sharing between 2 cores. My need is different.
I want declare a uint32_t variable which will be updated/written by one of the cores and read by another core. What is the memory address of SRAM which is common to both the cores? Can you share any example on this?