2023-05-12 04:05 PM
The SDRAM is 8MB, and starts at 0x60000000
I would like o share the first 1MB between the M4 and the M7 cores
void MPU_Config() {
MPU_Region_InitTypeDef MPU_InitStruct;
/* Disable the MPU */
HAL_MPU_Disable();
// Initialize SDRAM Start as shareable
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x60000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_1MB;
//MPU_InitStruct.SubRegionDisable = 0x00;
//MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Enable the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
I would like to know if the code above is the correct way to set up the shareable region.
Thanks for any help
2023-05-24 08:38 AM - edited 2023-11-20 05:34 AM
Hello @RSala.1
Could you explain why you disable the configuration of TEX field level. This parameter can be The TEX, C and B bits are used to define cache properties for the region, and to some extent, its shareability. They are encoded as per the following table as referenced in AN4838.
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