Hi there.
I'm working on some boards with an STM32F429VI, and for these boards we'd like to do some crystal startup testing to ensure the design is robust.
The previous test we've done is have the product power-cycle itself <n> times and ensure the board starts up. Both at high and low temperatures, and at high humidity.
While this test is decent, it doesn't really give any measurement of how much margin we have, and I'd prefer to actually measure the startup time.
We have an R&S ZD20 available. (Datasheet)
It has the following input structure, and is rated at 1MΩ 0.6pF loading across the diff input:
Looking around online for documentation on measuring crystal startup time, and it seems for HSE it should start up in a few ms.
The scope is set up for peak detection, to allow a large time-base to capture the startup sequence.
Probing is done as seen here:
The DUT doesn't have actual test points for this, it's probed either directly on the crystal, or across the load capacitors.
For TP3, the turn on time is ~225ms
For TP2, the turn on time is ~175ms
For TP1, the turn on time is ~6ms
My theory is this is because the probe, while very low loading, DOES load the crystal this slows the startup when probing on anything but the output of the crystal driver in the STM.
Doing gain margin calculations for our crystal (ABM3BAIG ABM3BAIG) we get a margin of 331 uA/V or a factor of 7.48, so theory wise we should be well within specs.
Below are the pictures of the crystal start up, in the order TP3, TP2, TP1
Oh and I did check if this had anything to do with power on, but 3v3 is on way before this, so the "kick" we see here is the crystal startup.
I realized that my question may not be entirely clear.
I'm curious if I'm going about measuring this correctly, and if my assumption on the difference is correct? I feel like it's a pretty huge difference.
Also, any guidance on what value I should expect? 6ms is still about double what I've read in other places of 3ms for MHz speed crystals.
