How to use a timer to stop another timer?

[XDong.1]

In the Reference Manual R0008, there is "Using one timer to start another timer" in Chapter 15.3.15. I want to know whether "use a timer to stop another timer" can be realized.

Besides, I want to stop the timer in a rising edge, so the gated mode can't be used. I don't want to use interrupt either because it causes some delay.

[waclawek.jan]

There's no direct way to do this.

Indirectly, you can trigger from the first timer a DMA transfer from memory to the other timer's CR1, containing the required value to stop the timer.

> I want to stop the timer in a rising edge

I don't understand what do you mean by this; a timing diagram would help if you want to discuss this further.

JW

[XDong.1]

In the gated mode (SMS = 101), a timer works when its TRGI is high. That is to say, a timer can be stoped in a falling edge of the output of another timer. So I think it difficult to stop the timer in a rising edge.

[berendi]

Although I don't understand either what exactly you want to do (why don't you just invert the output polarity of the master, or use another channel/synchronized third timer), here's something that might help

TIMx control register 1 (TIMx_CR1)

Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: [snip]

1: UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is

set or if a hardware reset is received from the slave mode controller.

You can use this mode to stop and reset the timer on the rising edge. (But I'm not 100% sure that it would work).

• Set counter and channel parameters (PSC, ARR, CC* etc), generate an update if necessary (TIM_EGR_UG)
• Set slave mode 100: Reset mode
• Set TIM_CR1_ARPE and TIM_CR1_UDIS
• Set ARR=0.
• Start the timer.

Now beacuse ARPE is set, ARR=0 will be effective first when reset is triggered by the master. Then ARR will become 0, and the timer is effectively stopped.

[XDong.1]

OK, thanks. I'll have a try later.

[XDong.1]

OK, thanks. I'll have a try later.