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How is PLL jitter measured in the STM32H7 datasheets?

Associate III

I'm considering using the internal PLL to generate a clock for a precision ADC. My sample rate is low, so it's possible this may work. I need less than 50 ps RMS phase period jitter.

Looking in the datasheet at the specs for PLL1, I'm having difficulty understanding what the specification for jitter means. For example, is it rms, or is it a min/max measured over a certain number of clock cycles? I'm even further confused because some of the measurements on PLL2 specify "+-ps", but on PLL1 it just says"ps".

I'm looking at an STM37H725.




ST Employee

Hello @tjdyhdsfeadgstdj ,

The PLL jitter in the STM32H7 datasheets is measured over a number of periods of the clock. Specifically, the measurement has been done for n=1, 10, 100, 1000 periods.

For long term jitter, the cumulative jitter for 1000 cycles is measured, and a typical value for this parameter is provided.

I shared this post that may help you: About STM32H7 PLL configuration and precision - STMicroelectronics Community

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