How can STM32F769 DMA controllers access the DTCM?

[arnold_w]

I am working with the STM32F769 microcontroller and I can see that a lot of DMA buffers are placed in DTCM in the source code I'm working with. Looking at the data sheet ( https://www.st.com/resource/en/datasheet/stm32f765bi.pdf ) page 20 I don't see a bus between the DMA controllers and the DTCM. Apparently it works so there must be a way for the DMA data to go to/from the DTCM, but how? Is it, in general, recommended to place DMA buffers in DTCM? I mean, just because it's close to the CPU doesn't mean it's close to the DMA peripheral.

[Bob S · Accepted solution]

I don't have the F76x ref man handy, but in the F74x/75x ref man, section 2.1.1 "Multi AHB BusMatrix" it says that there is a specific AHB slave port that provides general purpose DMA access to DTCM (but not ITCM).  This is shown in the system architecture diagram as the "AHBS" line coming into the top of the M7 core block along with the DTCM and ITCM lines.

[Piranha]

AHB slave port that provides general purpose DMA access to DTCM (but not ITCM)

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The bolded part is not true:

"The 32-bit AHB slave (AHBS) interface provides system access to the ITCM, D1TCM, and D0TCM."

https://developer.arm.com/documentation/ddi0489/f/memory-system/ahb-slave-interface

And here are some more details:

https://community.st.com/t5/other-tools-mcus/linker-file-bugs-in-lwip-http-server-examples-for-gcc/m-p/228691/highlight/true#M1270