Posted on August 15, 2012 at 16:55Hi,
I am using the STM32L151VC mpu and I have run into a problem in that a hard fault is being thrown by a seemingly innocuous bit of code inside the STM32L1xx_StdPeriph_Lib_V1.1 in the NVIC_Init() function. The line is line 146 from the file STM32L1xx_StdPeriph_Driver\src\misc.cas follows :
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
The hard fault is thrown by the central part of this which I have extracted out as follows :
/* Compute the Corresponding IRQ Priority --------------------------------*/
// tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
uint32_t *** = (SCB->AIRCR) & (uint32_t)0x700; // !!!!!!! Problem
tmppriority = (0x700 - ***)>> 0x08;
I have checked the disassembled line which seems completely innocuous :
ldr r3, [r3, #12]
r3 has the value 0xe000ed00 at the start of the instruction which agrees with the values for SCB->AIRCR from core_cm3.h. SCB is defined as 0xE000E000UL + 0x0D00UL, and AIRCR is the 4th uint32_t (ie offset 0x0C) defined in SCB_Type, also in core_cm3.h.
The output from the hard fault handler I am using is :
Hard fault handler - all numbers in hex :
R0 = 20001df4
R1 = 40013800
R2 = 40013800
R3 = e000ed00
R12 = 8001a95
LR [R14] = 8000b33 subroutine call return address
PC [R15] = 8000d7e program counter
PSR = 21000000
Bus Fault Address Reg, BFAR = e000ed0c
Configurable Fault Status Reg, CFSR = 8200
Hard Fault Status Reg, HFSR = 40000000
Debug Fault Status Reg, DFSR = 1
Auxiliary Fault Status Reg, AFSR = 0
Sys Hdlr, Ctrl & State Reg, SCB_SHCSR = 0
I assume I must be doing something wrong but can't see for the life of me what it is, any ideas greatefully received.
Thanks,
Mike
