GPIO-speed

[farbror_brydling]

Posted on January 03, 2011 at 09:41

GPIO-speed

[damh]

Posted on May 17, 2011 at 14:20

Your are writing to a cache register. It will change like any other register with 72MHz. The output circuit is scanning this register with its own frequency (<50MHz, in your case probably 36MHz) and changes the output according to the register value.

The output is depended on the asm code.

[farbror_brydling]

Posted on May 17, 2011 at 14:20

Thank you. I want to generate a clock to a shift register from C-code. What do you think would be a nice solution? Insert a delay between each write to the GPIO-pin?

[Tesla DeLorean]

Posted on May 17, 2011 at 14:20

Thank you. I want to generate a clock to a shift register from C-code. What do you think would be a nice solution? Insert a delay between each write to the GPIO-pin?

Depends on the max frequency of your shift register. Chances are you don't need any delay, as the speed at which you can toggle the pin are limited to your access speed to the GPIO registers. The 50 MHz for the IO pins refers to the strength of the drivers, the slew rate, ie how fast the edges are, not how fast you can actually toggle them. The SPI clocks and registers could also act as fast clock sources, and as shift registers. You could also use the timers to generate clocks. There are probably other solutions, but the problem isn't well defined.