Force FSMC to 16Bit

[dirk1]

Posted on December 13, 2009 at 17:52

Force FSMC to 16Bit

[dirk1]

Posted on May 17, 2011 at 13:33

Hi,

is there a way to force the FSMC to make 16Bit access for write cycles? I want to use two 8Bit SRAM an use them parallel to get a 16Bit memory. This was working perfect for the old STR710 derivates. But with the STM32F103 this seems not to work with 8Bit write access on the external SRAM. Working with two 8Bit SRAMs assumes that the controller makes only 16Bit write access. But the stm32 is massivley using the NBL lines and tries to write single Bytes. Is there a way to inhibit the 8Bit access on chip? I'm using the cypress cy7c1069 SRAM which has two chip select inputs. One signal low active and another high active. Is there a way to change the level of the NBL signals?

[gahelton12]

Posted on May 17, 2011 at 13:33

Use the NOR Flash setting instead of SRAM. The NOR Flash setting uses 16 bit access mode (either non-multiplexed or multiplexed). Refer to RM0008 Tables 89 and 90 and the NOR Flash timing diagrams starting at Figure 165. Using the NOR Flash settings eliminates the ''byte lane'' issues and allows straight 16 bit access.

Also, you won't be using the NBL signals anymore for 16 bit access. Chip select will be made with the NEx signals (active low). Since you have an active low chip select on the Cypress, tie NEx to your Cypress active low chip select and tie the other CS high.

[dirk1]

Posted on May 17, 2011 at 13:33

Thanks for the reply. I already saw that the timing charts for the NOR flash modes do not show the use of the NBL lines, but that could also be a mistake. I wonder if anywhere in the datasheet is the behaviour of the NBL lines described for mode B to D?

[gahelton12]

Posted on May 17, 2011 at 13:33

The ommisson of the NBL signals from the NOR timing diagrams is no mistake. They are not needed for these modes.

If you have two 8 bit SRAMs, they are treated as a single 16 bit access. D0-D7 will connnect to the SRAM data bus of one device while D8-15 will connect to the data bus of the second device. The NEx chip select output from the micro will connect to the chip selects of both SRAMs - That is, both devices will be selected simulataneously for both read and write operations. No byte lanes are necessary.

[gahelton12]

Posted on May 17, 2011 at 13:33

By switching to the NOR timing, you would be locked into 16 bit access since byte lanes are not available in this mode. If you want to have either byte or 16 bit access, the you want to stick with SRAM mode. Then the byte lanes can select individual bytes (or words) from your SRAM.

It is my understanding from the timing diagrams, that if you ask for a 16 bit access, then both byte lane signals are active and you read or write the 16 bit value in a single bus transaction (no penalty). If you are concerned with byte access, stick with SRAM mode.

[dirk1]

Posted on May 17, 2011 at 13:33

I wonder if it is possible, with this 16Bit setup, to write single Bytes. Writing a single Byte on an uneven address would require a read access on the even address first. Is the STM32 able to this?

I want to use the external SRAM also for debugging and I don't know if the code will always be 16Bit aligned..