2014-11-01 02:46 AM
I've noticed that the output of the clkout pin is very near the frequency I would expect when a external crystal is used as the pll source, but fluctuates a little as the CPU performs gpio operations.
When I configure the internal oscillator as the PLL source, the frequency is a bit off, which I expected, but under loads it shows very large changes in frequency. Is this expected for the clock out behavior, or is this likely to be a power issue with my layout? Any suggestions on how to go about tracking down the cause, assuming its abnormal?2014-11-01 02:47 AM
This is on the STM32F407
2014-11-01 03:17 PM
Can you please be more specific in terms of Hz?
The PLL is certainly one of the analog circuits most sensitive to power supply on the chip, and proper (as close to the pin as possible) decoupling of all power pins is simply a must. Some jitter is to be expected and may be supply-voltage dependent, but the long-term cycle count ought to be stable when a crystal/oscillator is used. The internal RC oscillator is chattering significantly even under stable supply, and I wouldn't really draw much conclusions from the output of that one. JW2014-11-01 05:32 PM
Ideally the supply/ground should be planes on the PCB, absent that nice thick traces. Make sure there is some bulk capacitance across the supply close to the chip (VDDA,VSSA), and most current is drawn by CMOS circuits as they switch, which will therefore manifest at CPU, PLL and peripheral clock frequencies. The core will be pulling from the VCAP pins.