2016-06-15 06:56 AM
I have an STM32F4xx device connected to NOR Flash on Bank 1. I am aware that NOR flash cannot Boot from Power-up, So a Boot Code from Internal Flash has to do some Init for the NOR Interface and then Jump. I need sample code or any Application Note which shows how to Config the NOR to execute code, how application to be Build i.e. the ROM address for Code if we are going to Remap the NOR to 0x0000 0000, How is Interrupt vector table addressed in this scenario, and also the Debug (I am using IAR and J-link). And also I have doubt that while CPU is fetching the instruction from NOR flash can it also perform a Write Operation on other sectors for Data storage. A Note on what all should be taken care in Boot and In application to get the Best performance will be great.
#nor-flash-code-execution2016-06-15 08:21 AM
I don't see that you're going to be able to map the External NOR to zero, or why that would be desirable.
The vector table can be placed at any 512-byte aligned address, and the code should be built for the native address that the NOR memory falls within the memory-map. You'd do this via the linker script or scatter file describing memory. I would probably avoid putting the vector table in NOR, but rather copy it from NOR into RAM, as the access to the memory is going to be significantly slower, and if you have interrupts (systick, etc) hitting all the time you're going to degrade the entire system performance. Remember the M3/M4 doesn't have any caching, the ART is a type of cache but is limited to FLASH, and not architectural.2016-06-16 09:48 PM
Hi clive1,
Thanks for your Inputs, What does the SYSCFG_MEMRMP register in SYSCFG Pheriperal has MEM_MODE[2:0] do this settings mention that External NOR is remapped to Zero when it is set to ''010'' what does it mean. To answer why it is desirable to remap the actual NOR address to zero is in some Application Note it was mentioned that External NOR Flash accessed by CPU through FMC is through system bus But NOT the I-Code & D-Code Buses, which is slower to boost this latency remapping the External NOR Flash to Zero will allow I-Code & D-Code Buses to get Access through FMC and get better performance. (Can you please make this sure?)It was really a useful info you gave about placing the Vector table in RAM to give more push to performance, I will try from my end thanks,Thanks,Bhuvanesh S2016-06-21 08:16 PM
Hi clive1,
Any thoughts? I am still waiting for your reply.Thanks,Bhuvanesh S