2010-09-03 12:56 PM
DMA Priorities and Associated Latencies
#dma2011-05-17 05:05 AM
Dear Brian,
You will find all details on STM32F10xx DMA inhttp://www.st.com/stonline/products/literature/an/13529.pdf
: Using the STM32F101xx and STM32F103xx DMA controller :2011-05-17 05:05 AM
STOne-32:
Thank you for the response and the link to the document. It appears that with 2 DMA channels, the highest priority DMA has to wait for the bus to clear before beginning its own transfer leading to a variable jitter time for DMA completion. The only time DMA is entirely predictable is if there is only 1 DMA channel configured.