DMA GPIO->SRAM test is not giving expected results

adrian5 · ‎2009-12-08

Posted on December 09, 2009 at 05:55

adrian5 · ‎2011-05-17

Posted on May 17, 2011 at 13:33

slawcus, I think blackfin is really too big a hammer to crack this nut. The objective is to scale down a video feed into a vague impression of the colours top, bottom and sides of the frame to create background illumination behind a TV screen. It's only really a home experiment.

Quote:

Indeed the same DMA request (generated by external input event) can be used to trigg two transfers from I/O to SRAM, accordingly from two differents GPIOs and accross two diffrents DMA channels.

I don't think you will need overlap mode in this case.

armmcu.engineer, I didn't realise that the same request could initiate two transfers! Now I realise that I haven't understood how DMA is linked to a timer - AN2548 configures DMA Channel 6 to transfer from GPIO to RAM and then enables Timer 3 DMA with:

/* Enable TIM3 DMA */

TIM_DMACmd(TIM3, TIM_DMA_CC1, ENABLE)

How does this specify DMA channel6? Put another way, if another DMA channel is configured for a different source/dest what command would enable it to be clocked from the same timer pin?

armmcu · ‎2011-05-17

Posted on May 17, 2011 at 13:33

Hi adrian2,

Sorry for the misleading I've caused :-[

What I've said before is not feasible with STM32 but for some old ST products (which I've used to work with).

Anyway I've found the folowing figure on STM32 documentation :It seems each DMA channel has some specifc periph requests to handel (this can explain your query)

As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel(only one request is served at a time)

Hence in your case when using two diffrents channels , you have to enable two diffrents DMA requests.I'm not sure if it's feasible to synchronise two diffrent timers on STM32.

Cheers.

tomas23 · ‎2011-05-17

Posted on May 17, 2011 at 13:33

Moreover, one DMA transfer has no option to grab 32-bit data - both FSMC and GPIOs offer 16-bit access only.

Grabbing data from two GPIO units doesn't help either, as DMA can access only one APB/RAM at the same time, two reasons:

1. GPIOs share the same APB, this blocks two DMAs running completely in parallel

2. one DMA cannot access two source addresses at the same time (two GPIO units)

zeetahhs · ‎2011-05-17

Posted on May 17, 2011 at 13:33

Could it be that the data is not flowing through the GPIOs fast enough?

A test would be to sample the clock and the data using the CPU and then see what you get.

tomas23 · ‎2011-05-17

Posted on May 17, 2011 at 13:33

Nope, the GPIOs can run at 72 MHz, but APB/AHB transaction takes 2-3 cycles, +1 per LDR, so you read at speed 18 M/s. You have only 12 registers for data, so either you interleave the read-outs with storing data to RAM, or do it later with bigger gap in reading.

Sum: DMA adds 5 cycles, APB/AHB bridge adds 2-3 cycles, CPU adds 1-3 cycles.