Dividing Timer

[LMorr.3]

I need advice on setting up a 'primary timer/clock' to toggle a an output pin for 20ms, at a user set frequency of anywhere from 16Millihertz to 16.65Hz ( approx ) with 16 bit resolution. ( user sets value from 0 to 10000 )

The primary timer/clock must also trigger 4 'secondary timers/clocks'.  Each secondary timer individually divides the primary timer frequency by a user set value of 1 to 16. ( slowing the frequency ) The user may change the division values while the primary timer is running. Eg. If the primary timer is running at 10Hz, dividing by 2 would produce 5Hz on a secondary output pin.  The result is 4 'secondary' clock outputs running at different frequencies based on the primary clock.

I currently using polling and track system ticks to build software timers and to calculate when to trigger one shot PWM to each output pin. The primary clock 'counter' is in turn divided by up to 16, to trigger secondary output clocks when counters reach division thresholds. I works 'ok' but I realize this may not be the best solution, and I want to find more of a hardware approach if possible.

Is there a better approach which would use mostly/only hardware timers? I'm thinking maybe looking into timers 'triggered' by other timers and other STM32 timer features I may have initially overlooked.

One issue I encountered was getting the primary hardware timer to run at low frequencies of 16Millihertz. I currently use software counters using sytem tick, and toggle the output pins ( one-time-pulse of 20ms ) in software instead of relying on hardware timers  to do the job. Do I need one timer to trigger the primary timer to get to that low of a frequency?

It would be preferable if I could just set PWM registers on the fly and keep clocks/outputs all in using peripheral timer features.

Thank you!

[Johi]

Hardware timers in the STM32 architecture are an ideal hardware solution for the task you propose.

Do notice that you can cascade them but start with a basic example.

See the RM reference manual for your processor for details related to the count and the capabilities.

[KnarfB]

The cascading you describe is called trigger mode and needs timers to be configured as master rsp. slave. Not sure if you find so many slave timers though. May trigger by SW from master's IRQ handler instead.

For low freq., you may use a 32-bit timer and maybe lower the freq. of the peripheral bus the timer is on.

hth

KnarfB

[waclawek.jan]

Which STM32?

JW

[LMorr.3]

I'm using STM32F373 at this time but can use other uC if required.

Update: I'm looking at maybe using 1 main hardware timer and have it trigger and increment the hardware counter registers for each secondary timer.  Each secondary timer would need to be synced with the primary since divided pulses will eventually 'meet up' again.  ( that is maybe where I can use the primary timer to trigger secondary timers somehow ? ) I would need to ensure I can get all timers running at low enough frequency to be up to 16 times slower than the primary timer.  

Another option I thought of: I could use the counter register of each secondary timer to set the division from 1 to 16, and set all the other timer values the same for all 5 timers so they all run at the same rate.   Is there a way to keep all 5 timers in sync?  ( use the primary to trigger other timers maybe? )

The other easier solution is to have 1 primary timer with its interrupt incrementing counter variables for each secondary timer and do one time pulses for secondary timers when their corresponding counters reach the division point.