Default Interrupt priority levels and no of levels?

[jonfs2000]

Posted on November 07, 2013 at 12:13

Hi,

I if will be great if some one clarify me the following, * What is the default interrupt priorities? When I read using either

priority4 = NVIC_GetPriority(UART4_IRQn);

or

priority4 = NVIC->

IP

[

EXTI4_IRQn

]; it always returns 0. * How many priority levels? On the RM0090 reference manual Pg249 NIVC features says '16 programmable priority levels', but Table 45. on priority column the level goes up to 88. Please explain me this. Also on PM0214 Programming manual, Pg201 4.3.7 Interrupt priority registers(NVIC_IPRx) it says '8 bit priority' field. Thanks John #interrupts-priority

[zzdz2]

Posted on November 07, 2013 at 18:21

* How many priority levels?

On the RM0090 reference manual Pg249 NIVC features says '16 programmable priority levels', but Table 45. on priority column the level goes up to 88. Please explain me this.It's like a hardwired subpriority.When multiple irqs occur at once and they all have the same priority level programmed, the one with lower number is served first.Also on PM0214 Programming manual, Pg201 4.3.7 Interrupt priority registers(NVIC_IPRx) it says '8 bit priority' field.Yes, it may be somewhat confusing, STM32 only uses 4 most significant bits of this field.

[glory_man]

Posted on February 13, 2014 at 09:02

Where can I find info about it - '' 4 most significant bits''?

In ''Cortex-M4 Devices Generic User Guide'' we have:    - The NVIC includes a Non Maskable Interrupt (NMI) that can provide up to 256 interrupt priority levels. PM0214 says:   - The NVIC includes a nonmaskable interrupt (NMI), and provides up to 256 interrupt priority levels. So, which option limits interrupts priorites to 16? I can't find in docs.

[zzdz2]

Posted on February 13, 2014 at 14:01

PM0214 Programming manual 

-> Core peripherals -> Nested vectored interrupt controller (NVIC) -> Interrupt priority registers (NVIC_IPRx) -> Table 47 :Each priority field holds a priority value, 0-255. The lower the value,the greater the priority of the corresponding interrupt. The processorimplements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.