Decoupling capacitors

[Diez.R.]

Posted on February 22, 2016 at 10:19

Hi all:

I am a software engineer with not much hardware experience. I am reading the following document: AN4488 Getting started with STM32F4xxxx MCU hardware development http://www.st.com/web/en/resource/technical/document/application_note/DM00115714.pdf 1) Section ''2.2 Power supply schemes'' says: ''The VDD pins must be connected to VDD with external decoupling capacitors: one single Tantalum or Ceramic capacitor (min. 4.7 μF typ.10 μF) for the package + one 100 nF Ceramic capacitor for each VDD pin.'' That would be a capacitor between each VDD pin and the power supply, or GND or VSS? See also below. 2) In ''Figure 11'' there is one capacitor between each VDD/VSS pair. These pairs are called VDD1/VSS1, VDD2/VSS2 and so on. The trouble is, there are no such names like ''VDD1'', ''VSS2'' and so on in the datasheet. I looked at the LQFP144 package for the STM32F40x we are using, and while most VDD/VSS do come in pairs, some do not. For example, VDD on pin 72 and VDD on pin 144 have no corresponding VSS pins. What should I do in those cases? 3) Section ''7.4 Decoupling'' says: ''In addition, each power supply pair should be decoupled with filtering Ceramic capacitors (100 nF) and one single Tantalum or Ceramic capacitor (min. 4.7 μF typ.10 μF) connected in parallel.'' Figure 27 does show a capacitor between two neighbouring VDD and VSS pins. I guess that sentece is not correctly phrased, and the 10 μF capacitor is not for each pair, but just one for the whole chip, right? Or do I need 2 capacitors per VDD/VSS pair? Are those capacitors between each VDD/VSS pair the same ones as described in part (1) [section 2.2] above? Thanks in advance,   rdiez

[John F.]

Posted on February 22, 2016 at 11:05

A multi-layer PCB is normally used with one plane reserved for ground (VSS).

(1) It's good practice to connect a 100 nF X7R capacitor from each VDD pin to the ground plane. Use the shortest possible path - normally direct to the pin on the component side and a via to the ground plane. (2) If the VDD and VSS are ''paired'', the via provides the connection of VSS to the ground plane. If not, the via just connects the capacitor to the ground plane. (3) The ''extra'' 4.7 uf min or 10 uF capacitors can be placed one on each side of the quad package ... so you'd use four. It's likely that your 3.3 V DC power supply will also have larger capacitors at its output. Consult the Data Sheet for whatever chip you use. Keep the ground plane as ''solid'' as possible. In other words, don't use that layer to run other tracks.

[Tesla DeLorean]

Posted on February 22, 2016 at 18:01

The 100nF decoupling capacitors are there to kill high frequency noise. So all VDD pins, decoupled to ground (plane). On 2-layer boards have adequate power/ground traces.

The low ESR uF bulk capacitors are there to supply instantaneous current. I'd suspect you want one of these close to the part, close to the internal regulator supplies (32 on the 64-pin). You'd also want a bulk capacitor close in to your own regulator.The F4's wants bulk capacitors on the VCAP pins close to the part. These are part of the 1.25V regulator circuit internally.

[re.wolff9]

Posted on February 23, 2016 at 09:24Maybe it helps to understand that the pinout of the F4xx CPU is an evolution from the ealier families F1xx, F2xx, and F3xx. Those didn't need VCAP. The VCAP pins on the earlier processors are ground. On F4xx those are repurposed as ''VCAP''. If I mount a non-F4xx processor on my board, I just place a solder-blob on the space for the capacitor to connect the pin to ground. Knowing that, there are simply four VDD/VSS pairs. (but one ''upgraded'' to VCAP/VDD). Maybe it's also useful to know that one of the VDD pins is now becoming VDD-IO for a group of IO pins instead of a pin that might power the chip. Further evolution of the pinout.