I'm not a hardware engineer, so apologies if this is a stupid question ...
I have two STM MCUs communicating over an open-drain line which has a pull-up resistor. Each MCU has a GPIO port connected to the line, and the ports are configured open-drain, no internal pull-up or pull-down. Software "bit bangs" the GPIO ports. Everything works.
(This is a simplified example for sake of the question. Real system has multiple open-drain lines and more than two MCUs connected to each.)
What happens if buggy or malicious software sets the ports to push-pull with one high and one low? This is a direct short from Vdd, through the high port's high-side transistor, across the line to the low port's low-side transistor, to ground. The transistors aren't power MOSFETs with milliohm RDS(on), and I can't find a spec in the datasheets, but maybe 10's of ohms (??), so still lots of current.
STM GPIO ports are typically rated for 8 mA (or 20 mA "with a relaxed V(OL)/V(OH)"). What happens next?
- The port is destroyed?
- The whole chip is destroyed?
- Some safety circuit shuts down the port (or the whole chip)?
Assuming #1 or #2, should I put series resistors on the ports to limit the current to a safe range? 3.3V divided by 8 mA equals 412.5 ohms. Maybe divided by two because one on each port, in series. But maybe increased because multiple ports driving the line in parallel.
This will decrease the noise immunity of the ports because voltage drops across the resistors will lower the "1" level (and raise "0"?). But the input impedance of the ports should be fairly high (again can't find a spec except for the ADC ports), maybe 10's of kOhms, so a large ratio voltage divider and thus not a problem?
What's standard practice for this? Thanks for any advice.
