confusing about the regiser SYSCFG_CFGR3?

[hguo.11]

mcu:STM32L071RBTx

questions in the reference manual ：9.2.3 Reference control and status register (SYSCFG_CFGR3)

Bit 8 ENBUF_VREFINT_ADC: VREFINT reference for ADC enable bit

This bit is set and cleared by software (only if REF_LOCK not set).

0: Disables the buffer used to generate VREFINT reference for the ADC.

1: Enables the buffer used to generate VREFINT reference for the ADC.

as is described above ，when the bit ​ENBUF_VREFINT_ADC is set one，the adc ref+ =VREFINT??? in fact is not，so what is the real meaning of “Enables the buffer used to generate VREFINT reference for the ADC.�?？？？how “the buffer�?work？

[TDK]

VREFINT is never VREF+.

VREFINT is a ~1.2V signal that you can use to estimate what VREF+ is. If you want to read it through an ADC, you need to enable the VREFINT buffer using that bit (among other things).

Read the "Internal voltage reference (VREFINT)" section in the reference manual.

[hguo.11]

First of all, thank you for your answer�?，what confused me is the result when the ENBUF_VREFINT_ADC bit is set，According to my experiment，when the bit is set，It has no effect on my ADC application。that is to say when the bit is reset ，i still can read the 1.2v through the ADC_IN17 。so what is the real meaning of “ENBUF_VREFINT_ADC ：1，Enables the buffer used to generate VREFINT reference for the ADC.�?？？