@clive1 - re; Alternate Function Reply

[troneeee]

Posted on August 26, 2016 at 07:48

clive1,

I have attempted repeatedly to reply to your post to me. STM server sw apparently, has a bug which prevents me from posting replies. However, I can post 'new' messages, so here is a somewhat tardie reply. Thank you for your understandable answer and example. It works, hee hee, and its clear to me how it works...:) I have another question which I can't find an answer for in any of the manuals I have.  Regarding setting the I2C_CCR frequency settings which the manual (RM00368) identifies as being reliant upon ''fPCLK1'', which as I said before, I can't find the module to which that label references in either the F401 datasheet or the ref_man.  I2C clk speed Smode freq ''must be at least 2MHz while Fm must be at least 10MHz''. In attempting to verify that my code meets that spec, I can't find the module or the register to which it is affiliated?  I pray that my questions are not too 'dummie'? I did see a very brief statement re; APB1 bus, but in looking at the RCC module subsystem dwg I see no reference to the fPCLK1 label. (that dwg is pretty poor for other reasons too, IMO.) In any case thanks again and in advance for your time. armor ps, fyi, I was the debug eng'r for the prototype L2C control-segment digital-signal-processor (of the 32 rack-mount units deployed in DoD bunkers) that measure precision GPS constellation timing and control selected elements of the selective-availability of the constellation, for the prime.

[Tesla DeLorean]

Posted on August 26, 2016 at 11:30

The APB clocks are often referred to as PCLK, the frequency of those as fPCLK. The I2C peripherals tend to live in the slower clock domain APB1. The STM32 uses very simplistic counter chains to do division, so most everything divides in an integer fashion, more sophisticated designers have used adders for decades to get fractional division with very minimal jitter/modulation.

So the APB clock sources tend to constrain how fast the buses clock through the dividers in each peripheral. ie SPI, USART, I2C etc. Not a big user of the I2C bus, seem to recall there being two clocking schemes, one using 25 clocks and not promising 50/50 duty, and these tend to require specific APB clocks as starting points to get exact clocks at SCL.The more clocks consumed at a bit level require much higher clocks at the peripheral level to achieve the right timing. I've had to reconfigure the frequency plan of the STM32 on one of my boards to get a specific clock frequency out of a TIM unit. Very frustrating at times.