Clarification on the NBL[3:0] when using 8 bit SDRAM on the STM32F429 in 8 bit mode.

[Barber.Mark]

I am using the STM32F429 and interfacing some SDRAM which i have done before with no problem but in 16 bit mode. So the NBL0 and NBL1 where connected to the SDRAM and the system works very well.

Due to needing a few extra pins for general IO i am dropping the SDRAM back to 8 bits. Here is where i am a little unsure. When using 16 bits NBL0 connected to the SDRAM DQML and NBL1 connected to SDRAM DQMH. All good makes sense. If i am using 8 bits then you would assume that i connect NBL0 to DQM (formly DQMH) however this does not look right based on some of the example schematics. It looks like in 8 bit mode i need to connect NBL1 to DQM. The data sheet is woefully inadequate in the SDRAM section relating to the use of the NBL (Output Byte Mask) pins, at least i have been unable to find definitive details.

regards

Mark

[Tesla DeLorean]

Seems odd we'd see two similar post within a day or so

https://community.st.com/s/question/0D50X00009fECmtSAG/connecting-stm32f7-fmc-with-sdram-and-8-bit-data-bus

Talk to the FAE supporting your design, or open an Online Support request.

https://www.st.com/content/st_com/en/support/support-home.html

For a few extra IO, consider I2C IOE devices (IO Expanders)

[AShch.2]

Could ST engineers please confirm if it's OK to ground 8-bit SDRAM DQM pin?