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Can anybody help me how to translate this for my nucleo?

Myilm.1
Associate II
 
21 REPLIES 21

Bus speed is going to inherently limit speed at which samples are delivered, you can adapt the table to have less samples per cycle, or index with a wider step interval

void output_dac_sin_x3(void)
{
  int i = 0;
  while(1) // Continous
  {
    HAL_StatusTypeDef status = HAL_I2C_Mem_Write(&I2CHandle, DAC_ADDR, DAC_CHANNEL, I2C_MEMADD_SIZE_8BIT, (void *)&SinLUT[i], 1, 100);
 
    if (status != HAL_OK) puts("Argh!");
 
    i = (i + 3) % sizeof(SinLUT); // step table
  }
} // sourcer32@gmail.com

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For the 33.61 Hz, and 256 samples per cycle, the DAC is being sent samples at 8.6 Ksps.

Figure that's about 5 byte times of I2C traffic at 400 KHz

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