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Lukasz Przenioslo
Lukasz Przenioslo
Associate III
October 20, 2015
Question

Calculating DMA ADC conversion time

  • October 20, 2015
  • 6 replies
  • 1483 views
Posted on October 20, 2015 at 14:32

Hello there,

I am having problem calculating the exact conversion time of ADC when using DMA ring buffering.

I was trying to find it in the STM32F4 datasheet but didnt find it.

I was trying to deduce it out using scope (toogle a pin each time interrupt is handled) but it doesnt seem right and it seem to be not linear.

My system clock is 168 Mhz. I believe it gives 48 Mhz peripheral clock. I am using 12 bit adc which is 15 cycles. Now when I start the DMA ADC cycle to measure only 1 time I get 5.7 us time. For 10 measures I get 11.4 us and 28.4 us for 20.

Is there an equasion to be able to calculate it?
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    6 replies

    Tesla DeLorean
    Tesla DeLorean
    Guru
    October 20, 2015
    Posted on October 20, 2015 at 15:27

    12+3 = 15 of whatever APB/Prescale cycles. But that's also pretty fast. I'd benchmark a circular buffer of 1000 samples, in continuous mode.

    I'm not a fan of grinding the ADC like that, but rather pacing it with a timer and a rate I choose.

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    Lukasz Przenioslo
    Lukasz PrzeniosloAuthor
    Associate III
    October 20, 2015
    Posted on October 20, 2015 at 16:30

    Why not? Are there downsides from calculating time depending on the ADC conversion?

    Tesla DeLorean
    Tesla DeLorean
    Guru
    October 20, 2015
    Posted on October 20, 2015 at 16:42

    Because sampling at a specific frequency is generally more useful than playing games with the sample time and conversion time, and processor frequency, to hit specific rates.

    Also it's going to be impossible to process/store the data in any meaningful way. If you're processing every value with interrupts and low latency (time from sample to processing) you're going to hit the wall on processing long before you hit the wall on acquisition.

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    Lukasz Przenioslo
    Lukasz PrzeniosloAuthor
    Associate III
    October 20, 2015
    Posted on October 20, 2015 at 16:54

    I just created an alghoritm that works like this:

    User decides at what frequency he would like the DMA interrupts to occur. Lets say 10 kHz.

    Then a function calculates (taking underconsideration all timing parameters) how many samples will the DMA be able to store between interrupts. Thanks to this, sampling occurs in a regular cycles and I need to handle only 1 interrupt intead of more periodic interrupts.

    So for 10kHz frequency I am able to store 70 samples of 12 bit. Every ADC conversion finished interrupt I hadle the 70 samples (for example calculate average). Is this wrong?

    Tesla DeLorean
    Tesla DeLorean
    Guru
    October 20, 2015
    Posted on October 20, 2015 at 17:00

    You're free to use the ADC however you see fit, I just said I'm not a fan of grinding the ADC in a continuous mode, with the lowest sample rate, at a rate dependent on the current cpu/bus speeds.

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    Lukasz Przenioslo
    Lukasz PrzeniosloAuthor
    Associate III
    October 20, 2015
    Posted on October 20, 2015 at 17:03

    I understand. Thank you for info.

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