Address swapping of SDRAM

[shashank78Khandve]

Hi ST Community,

I am working on STM32H563 with external SDRAM connected through FMC.

I am trying to use:

• heap in SDRAM
• global variables in SDRAM
• execution/data access from SDRAM
• DCACHE enabled

Current SDRAM mapping:

0xC0000000

I noticed that in STM32F7/H7 examples there is support for:

HAL_REMAPMEMORY_FMC_SDRAM()

which remaps FMC SDRAM memory regions internally.

I found this in STM32F7 HAL:

__HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()

But on STM32H563 I cannot find any equivalent remap mechanism or SYSCFG macro.

My questions are:

1. Is there any equivalent SDRAM remap functionality available on STM32H563 / STM32H5?
2. Is SDRAM fixed permanently at 0xC0000000 on STM32H5 architecture?
3. Does STM32H5 treat SDRAM at 0xC0000000 differently regarding:

• DCACHE
• burst accesses
• MPU memory attributes
• speculative accesses

1. Are there any special MPU/DCACHE recommendations for using:

• malloc()/calloc() heap in SDRAM
• .bss/.data sections in SDRAM
• execution from SDRAM

Current observations:

• SDRAM works correctly when DCACHE is disabled
• malloc(), memset(), counters, global variables all work properly without DCACHE
• When DCACHE is enabled, SDRAM accesses become unstable/fail
• Tried both cacheable and non-cacheable MPU attributes
• SDRAM configured as Normal Memory
• FMC SDRAM initialization sequence follows standard HAL sequence

I want to understand whether there is any architectural difference between STM32F7/H7 and STM32H5 regarding FMC SDRAM mapping and DCACHE interaction.

Any guidance or reference examples for STM32H563 SDRAM + DCACHE would be very helpful.

Thank you.

[mƎALLEm]

Hello,

STM32H5 has different approach vs STM32F7 and STM32H7 regarding the cache. No SDRAM swap on STM32H5.

You can refer to the AN5872 "Introduction to the system architecture and performance in the STM32H5 MCUs" especially the section 3.3 Cache features.