ADC with DMA Half Conversion complete and Conversion complete callback not aligned.
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2018-12-25 12:17 PM
Hello,
i set stm32f103c8 adc1 at 12mhz . Main clock is 8Mhz * 9 = 72Mhz.
i use ADC_SAMPLETIME_7CYCLES_5 so 12.5 + 7.5 = 20cycle = 600ksps.
i set dma circular continuous mode with 1000 element buffer.
i can receive half and conversion complete interrupts , conversion complete interrupt frequency is very precisely 600hz ,however half conversion complete interrupt frequency is has such pattern ; 600hz ---> 598.6hz ---> 601.3hz ---> 600hz ---> 598.6hz .... so on.
what could be reason ?
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ADC
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DMA
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STM32F1 Series
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2018-12-25 4:08 PM
Hard to say without more detail and investigation. Rather an old part
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