ADC does not work. There is no data in the receive buffer.

[Alex Golubev]

Hello.

I want to run the ADC to transfer data through the DMA to the RAM buffer.

What did you do:

void initADC(void)
{
	DMAMUX1_Channel0->CCR = (9 << DMAMUX_CxCR_DMAREQ_ID_Pos); 
 
	DMA1_Stream0->CR &= ~DMA_SxCR_EN; 
	while(DMA1_Stream0->CR & DMA_SxCR_EN); 
	DMA1_Stream0->CR = DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_CIRC | DMA_SxCR_DIR_0;
	DMA1_Stream0->NDTR = 5;
	DMA1_Stream0->PAR = (uint32_t)&ADC1->DR; 
	DMA1_Stream0->M0AR = (uint32_t)&bufAdcData; 
	ADC1->CR &= ~ADC_CR_DEEPPWD; 
	while(ADC1->CR & ADC_CR_DEEPPWD); 
	ADC1->CR |= ADC_CR_ADVREGEN; 
	while(!(ADC1->ISR & (1<<12)));
 
	ADC12_COMMON->CCR = ADC_CCR_VBATEN
				| ADC_CCR_TSEN
				| ADC_CCR_VREFEN
				| ADC_CCR_PRESC_0 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_2
				| ADC_CCR_CKMODE_0; 
 
	ADC1->DIFSEL = 0;
 
	ADC1->CR |= ADC_CR_ADEN;
	while(ADC1->IER & ADC_ISR_ADRDY);
 
	ADC1->CR |= ADC_CR_ADCAL;
	while(!(ADC1->CR & ADC_CR_ADCAL)); 
 
	ADC1->CFGR = ADC_CFGR_AUTDLY | ADC_CFGR_JQDIS | (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0) | ADC_CFGR_DISCEN | ADC_CFGR_CONT | ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0;
	ADC1->CFGR2 = 0;
 
	ADC1->SMPR1 = ADC_SMPR1_SMP9_2 | ADC_SMPR1_SMP3_2; 
	ADC1->SMPR2 = ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP15_2; 
 
	ADC1->PCSEL = ADC_PCSEL_PCSEL_19 | ADC_PCSEL_PCSEL_18 | ADC_PCSEL_PCSEL_15 | ADC_PCSEL_PCSEL_9 | ADC_PCSEL_PCSEL_3; 
 
	ADC1->LTR1 = 0x00; 
	ADC1->LTR2 = 0x00; 
	ADC1->LTR3 = 0x00; 
	ADC1->HTR1 = 0x00; 
	ADC1->HTR2 = 0x00; 
	ADC1->HTR3 = 0x00; 
 
	ADC1->SQR1 = (ADC_SQR1_SQ1_1 | ADC_SQR1_SQ1_0)
				| (ADC_SQR1_SQ2_3 |  ADC_SQR1_SQ2_0)
				| (ADC_SQR1_SQ3_3 | ADC_SQR1_SQ3_2 | ADC_SQR1_SQ3_1 | ADC_SQR1_SQ3_0)
				| (ADC_SQR1_SQ4_4 | ADC_SQR1_SQ4_1)
				| (ADC_SQR1_L_2 | ADC_SQR1_L_0); 
 
	ADC1->SQR2 = (ADC_SQR2_SQ5_4 | ADC_SQR2_SQ5_1 | ADC_SQR2_SQ5_0); 
	ADC1->SQR3 = 0; 
	ADC1->SQR4 = 0; 
 
	DMA1_Stream0->CR |= DMA_SxCR_EN;
	while(!(DMA1_Stream0->CR & DMA_SxCR_EN)); 
 
	MODIFY_REG(GPIOA->MODER, GPIO_MODER_MODE3, 0x3 << GPIO_MODER_MODE3_Pos); 
	MODIFY_REG(GPIOA->MODER, GPIO_MODER_MODE4, 0x3 << GPIO_MODER_MODE4_Pos); 
	MODIFY_REG(GPIOA->MODER, GPIO_MODER_MODE5, 0x3 << GPIO_MODER_MODE5_Pos); 
	MODIFY_REG(GPIOA->MODER, GPIO_MODER_MODE6, 0x3 << GPIO_MODER_MODE6_Pos); 
	MODIFY_REG(GPIOB->MODER, GPIO_MODER_MODE0, 0x3 << GPIO_MODER_MODE0_Pos);
 
	MODIFY_REG(GPIOA->OSPEEDR, GPIO_OSPEEDR_OSPEED3,0x0 << GPIO_OSPEEDR_OSPEED3_Pos); 
	MODIFY_REG(GPIOA->OSPEEDR, GPIO_OSPEEDR_OSPEED4,0x0 << GPIO_OSPEEDR_OSPEED4_Pos); 
	MODIFY_REG(GPIOA->OSPEEDR, GPIO_OSPEEDR_OSPEED5,0x0 << GPIO_OSPEEDR_OSPEED5_Pos);
	MODIFY_REG(GPIOA->OSPEEDR, GPIO_OSPEEDR_OSPEED6,0x0 << GPIO_OSPEEDR_OSPEED6_Pos); 
	MODIFY_REG(GPIOB->OSPEEDR, GPIO_OSPEEDR_OSPEED0,0x0 << GPIO_OSPEEDR_OSPEED0_Pos);
 
	MODIFY_REG(GPIOA->PUPDR, GPIO_PUPDR_PUPD3, 0x00 << GPIO_PUPDR_PUPD3_Pos); 
	MODIFY_REG(GPIOA->PUPDR, GPIO_PUPDR_PUPD4, 0x00 << GPIO_PUPDR_PUPD4_Pos); 
	MODIFY_REG(GPIOA->PUPDR, GPIO_PUPDR_PUPD5, 0x00 << GPIO_PUPDR_PUPD5_Pos); 
	MODIFY_REG(GPIOA->PUPDR, GPIO_PUPDR_PUPD6, 0x00 << GPIO_PUPDR_PUPD6_Pos); 
	MODIFY_REG(GPIOB->PUPDR, GPIO_PUPDR_PUPD0, 0x00 << GPIO_PUPDR_PUPD0_Pos); 
 
	MODIFY_REG(GPIOA->AFR[0], GPIO_AFRL_AFSEL3, 0x0 << GPIO_AFRL_AFSEL3_Pos); 
	MODIFY_REG(GPIOA->AFR[0], GPIO_AFRL_AFSEL4, 0x0 << GPIO_AFRL_AFSEL4_Pos); 
	MODIFY_REG(GPIOA->AFR[0], GPIO_AFRL_AFSEL5, 0x0 << GPIO_AFRL_AFSEL5_Pos); 
	MODIFY_REG(GPIOA->AFR[0], GPIO_AFRL_AFSEL6, 0x0 << GPIO_AFRL_AFSEL6_Pos); 
	MODIFY_REG(GPIOB->AFR[0], GPIO_AFRL_AFSEL0, 0x0 << GPIO_AFRL_AFSEL0_Pos); 
 
	ADC1->CR |= ADC_CR_ADSTART;
}

Generator initialization:

	PWR->CR3 = PWR_CR3_LDOEN; 
	PWR->D3CR = PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0;
	while (!(PWR->D3CR & PWR_D3CR_VOSRDY)); 
	SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); 
	PWR->CR1 = PWR_CR1_ALS_LEV3 | PWR_CR1_AVDEN | PWR_CR1_SVOS_1 | PWR_CR1_DBP | PWR_CR1_PLS_LEV6 | PWR_CR1_PVDEN; 
	PWR->CPUCR = PWR_CPUCR_RUN_D3; 
	RCC->CR |= RCC_CR_HSEON; 
	while (!(RCC->CR & RCC_CR_HSERDY)); 
	RCC->BDCR |= RCC_BDCR_LSEDRV_0 | RCC_BDCR_LSEDRV_1;
	RCC->BDCR |= RCC_BDCR_LSEON;
	while (!(RCC->BDCR & RCC_BDCR_LSERDY)); 
	RCC->PLLCKSELR |= 0x2 << RCC_PLLCKSELR_PLLSRC_Pos; 
	RCC->CR &= ~RCC_CR_PLL1ON;
	while (RCC->CR & RCC_CR_PLL1RDY);
	RCC->PLLCKSELR |= RCC_PLLCKSELR_DIVM1_0; 
	RCC->PLLCFGR &= ~RCC_PLLCFGR_PLL1VCOSEL; 
	RCC->PLLCFGR |= RCC_PLLCFGR_PLL1RGE_3; 
	RCC->PLLCFGR &= ~RCC_PLLCFGR_PLL1FRACEN;
	RCC->PLL1FRACR = 0; 
	RCC->PLLCFGR |= RCC_PLLCFGR_DIVP1EN | RCC_PLLCFGR_DIVQ1EN | RCC_PLLCFGR_DIVR1EN;
	RCC->PLL1DIVR = ((2 - 1) << RCC_PLL1DIVR_P1_Pos)
			| ((60 - 1) << RCC_PLL1DIVR_N1_Pos)
			| ((20 - 1) << RCC_PLL1DIVR_Q1_Pos)
			| ((10 - 1) << RCC_PLL1DIVR_R1_Pos); 
	RCC->CR |= RCC_CR_PLL1ON; 
	while (!(RCC->CR & RCC_CR_PLL1RDY)); 
 
	RCC->CR &= ~RCC_CR_PLL2ON; 
	while (RCC->CR & RCC_CR_PLL2RDY); 
	RCC->PLLCKSELR |= RCC_PLLCKSELR_DIVM2_0
	RCC->PLLCFGR &= ~RCC_PLLCFGR_PLL2VCOSEL;
	RCC->PLLCFGR |= RCC_PLLCFGR_PLL2RGE_3; 
	RCC->PLL2FRACR = 0x00; 
	RCC->PLLCFGR &= ~RCC_PLLCFGR_PLL2FRACEN; 
	RCC->PLL2DIVR = ((10 - 1) << RCC_PLL2DIVR_P2_Pos) | ((50 - 1) << RCC_PLL2DIVR_N2_Pos);
	RCC->PLLCFGR |= RCC_PLLCFGR_DIVP2EN; 
	RCC->CR |= RCC_CR_PLL2ON; 
	while(!(RCC->CR & RCC_CR_PLL2RDY)); 
	RCC->CR &= ~RCC_CR_PLL3ON; 
	while (RCC->CR & RCC_CR_PLL3RDY); 
	RCC->PLLCKSELR |= RCC_PLLCKSELR_DIVM3_0;
	RCC->PLLCFGR &= ~RCC_PLLCFGR_PLL3VCOSEL; 
	RCC->PLLCFGR |= RCC_PLLCFGR_PLL3RGE_3; 
	RCC->PLL3FRACR = 0x00; 
	RCC->PLLCFGR &= ~RCC_PLLCFGR_PLL3FRACEN; 
	RCC->PLL3DIVR = ((10 - 1) << RCC_PLL3DIVR_P3_Pos) | ((50 - 1) << RCC_PLL3DIVR_N3_Pos); 
	RCC->PLLCFGR |= RCC_PLLCFGR_DIVP3EN; 
	RCC->CR |= RCC_CR_PLL3ON; 
	while (!(RCC->CR & RCC_CR_PLL3RDY)); 
	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY,FLASH_ACR_LATENCY_4WS); 
	MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ,FLASH_ACR_WRHIGHFREQ_1);
	MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE,RCC_D1CFGR_D1PPRE_2);
	MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1,RCC_D2CFGR_D2PPRE1_2);
	MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2,RCC_D2CFGR_D2PPRE2_2);
	MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE,RCC_D3CFGR_D3PPRE_2);
	MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE,RCC_D1CFGR_HPRE_3);
	MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE,0x0 << RCC_D1CFGR_D1CPRE_Pos);
	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW,0x3 << RCC_CFGR_SW_Pos); 
 
	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL_Msk, RCC_BDCR_RTCSEL_0);
    MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCEN_Msk, RCC_BDCR_RTCEN);
    MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL_Msk, 0x00 << RCC_D2CCIP2R_USART28SEL_Pos); 
    MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL_Msk, RCC_D2CCIP2R_USBSEL_0); 
	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, 0 << RCC_D3CCIPR_ADCSEL_Pos);
	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, 0 << RCC_D2CCIP2R_USART16SEL_Pos); 
	RCC->AHB2ENR |= RCC_AHB2ENR_SRAM1EN;
	RCC->AHB2ENR |= RCC_AHB2ENR_SRAM2EN;
	RCC->AHB2ENR |= RCC_AHB2ENR_SRAM3EN;
 
	RCC->AHB1ENR |= RCC_AHB1LPENR_DMA1LPEN; 
	while (!(RCC->AHB1ENR & RCC_AHB1LPENR_DMA1LPEN)); 
	RCC->AHB1ENR |= RCC_AHB1ENR_ADC12EN; 
	RCC->AHB4ENR |= RCC_AHB4ENR_CRCEN;
	RCC->APB1LENR |= RCC_APB1LENR_USART3EN; 
	while (!(RCC->APB1LENR & RCC_APB1LENR_USART3EN)); 
	MODIFY_REG(RCC->CFGR,RCC_CFGR_MCO2, 0x1 << RCC_CFGR_MCO2_Pos); 
	MODIFY_REG(RCC->CFGR,RCC_CFGR_MCO2PRE, 0xf << RCC_CFGR_MCO2PRE_Pos);