2025-06-23 3:05 AM - last edited on 2025-06-23 3:31 AM by Andrew Neil
Dear STMicroelectronics Support Team,
I am encountering an issue with ADC calibration on the STM32N657 microcontroller. Despite multiple attempts, the calibration process consistently fails. Below are the details of my setup and observations for your reference:
ADC: ADC1, Channel 1
Reference Voltage:
VREF+: External 1.8V (measured 1.76V)
VREF-: Ground
Other: Enabled ICache/DCache, GPIO, USART1, and system isolation.
Initialization Code:
SCB_EnableICache();
SCB_EnableDCache();
HAL_Init();
MX_GPIO_Init();
MX_ADC1_Init();
MX_USART1_UART_Init();
SystemIsolation_Config();
// Debug: Check registers post-init
printf("Post-Init ADC_CR: 0x%08lX\r\n", hadc1.Instance->CR); // Output: 0x00000000
printf("Post-Init ADC_ISR: 0x%08lX\r\n", hadc1.Instance->ISR); // Output: 0x00000000
// Explicit MSP init (debug)
HAL_ADC_MspInit(&hadc1);
printf("Post-MSP ADC_CR: 0x%08lX\r\n", hadc1.Instance->CR); // Output: 0x00000000
printf("Post-MSP ADC_ISR: 0x%08lX\r\n", hadc1.Instance->ISR); // Output: 0x00000000
// Attempt calibration
HAL_StatusTypeDef status = HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED);
if (status != HAL_OK) {
printf("Calibration Failed. CR: 0x%08lX, ISR: 0x%08lX\n",
hadc1.Instance->CR, hadc1.Instance->ISR); // CR: 0x00000001, ISR: 0x0000000B
while(1);
}
Register States:
After initialization, and remain , suggesting ADC is not enabled.ADC_CRADC_ISR0x00000000
Post-calibration failure:
ADC_CR = 0x00000001 (ADEN bit set, but no further activity).
ADC_ISR = 0x0000000B (Flags: + + ).ADRDYEOSEOC
Calibration Outcome:
Always fails with .HAL_ERROR
Why do and stay zero after initialization? Is the ADC not properly enabled?ADC_CRADC_ISR
Could the external reference voltage (1.76V, slightly below nominal 1.8V) cause calibration failure?
Are there known errata or configuration steps specific to STM32N657 for ADC calibration?
CubeMX Configuration:
Single-ended mode, 12-bit resolution, software trigger.
No DMA/IRQ, scan mode disabled.
Troubleshooting Attempts:
Verified clock configuration (ADC clock ≤ max limit).
Checked VDDA/VREF+ stability with oscilloscope.
I would greatly appreciate any insights or suggestions to resolve this issue. Please let me know if further details are required.
Best regards,
dw1