2009-02-25 05:19 AM
Active High and active low GPIO config
2011-05-17 04:04 AM
I need to give active low and high signals to the XILINX CPLD from my processor. I am unsure how the GPIO's need to be configured.
Does this work? For active low GPIO_WriteBit(GPIOB,GPIO_Pin_10,Bit_RESET); For active high GPIO_WriteBit(GPIOB,GPIO_Pin_10,Bit_SET); Also GPIO's are configured as Output_OD. Please let me know if that is the right way to go. Thanks!2011-05-17 04:04 AM
What voltage are the CPLD inputs? Do they have pull up or pull down resistors or are the just floating?
Output_OD would be used only is the CPLD inputs have pull up resistors.2011-05-17 04:04 AM
Hi siddj;
As said by trevor, to work with Output OD, each GPIO has to be pulled-up by a resistor (externally implemented or embedded in the CPLD). Otherwise you'll never obtain a high level seen by your CPLD. Why you don't use the output push-pull configuration?2011-05-17 04:04 AM
M3allem-
You/I have tried to assist in a related post. Suspect that this fellow seeks to obtain ''bi-directional'' Data-Bus operation between his STM32 and his CPLD. Now STOne-32 earlier/other post suggested the use of open drain. Like you - I believed push-pull. Of course what you say about pull-up Rs with open drain is true. I'm still curious on the benefits/performance/trade-offs between ''push-pull and open-drain'' - as regards a ''bi-directional'' bus design. It seems that one ''asks for trouble'' using push-pull on both sides. Some mechanism must be designed so that only one device is actively in the output mode. In the olde days of CPUs with separate ADR/DATA buses we simply daisy chained the micro D-bus to each memory/accessory - NO pull-ups were involved! (and clearly - I did not pay enough attention to HOW this worked - we just conveniently used it...)