Posted on May 17, 2011 at 12:41Does anyone see any problems with the following:
I have 40+ nodes sharing info using fast RS-232. Any node may transmit to any other node. A controller node maintains order.
Interconnect uses RS-485 differential line drivers. This is one signal path. From the software viewpoint TX & RX are tied together.
My plan . . .
Use USART#1 at 4.5M baud with DMA.
Every data packet contains a destination address.
Every node receives every data packet.
Packets range in length from 4 to 100 bytes.
I could use an interrupt per byte at this rate. I have 160 72MHz clocks per byte. The 24 clock Cortex ISR overhead leaves enough time to do what is needed. My take: it’s doable but not nice. I plan to use DMA.
Packet sender –
*Uses DMA
*Has interrupt on TC (Transmission Complete)
*Interrupt sets SBK (Send Break)
*Reset whatever to receive next transmission
Packet receivers –
*Use DMA
*Interrupts on LDB (LIN Break Detected)
*Reset whatever to receive next transmission
*Decode destination address
This is the first RS-232 I have used with TC. This looked to be a real plus in my setup. It is useful because I have to tell the RS-485 h/w to stop transmitting. All data shifted out is the right time to do this. But then we have the break needed at the end of every transmission. How do I know when that is done? Set SysTick for 13 baud clocks? (13*16 = 208 72MHz clocks. Then subtract 12 for ISR overhead.)
I can’t tell from the docs. Do I get another TC after the break finishes? Could I interrupt on the TX pin going high?
OR WOULD THIS WORK?
Or would idle line detection work to signal packet received. My system will not have enough DMA going on such that DMA access would be slowed by any more than 2 or 3 baud clocks. That and the TX holding register assure a continuous data stream.
