1-bit gaps in mid-serial transmit. Transmit Complete flag true.

[RSonn.706]

I am using Half-Duplex to network 3 "BluePills" (STM32F103C8).  

There is one master, and two slaves.  The master sends out a request with a slave identifier prefix.

The slaves receive all messages from master and all responses from the other slave, and ignore messages with wrong prefix.

Each time a device transmits (13 bytes), I have it wait until the Transmit Complete flag is true, and then I enable receive mode to monitor for a reply.  MY PROBLEM is that occasionally there is a 1-bit duration gap in the transmit data between bytes in mid-transmission.  During this 1-bit gap, the Transmit Complete flag is (wrongly) set to true.

My transmit code is from the HardwareSerial library in the ststm32 arduino framework

Serial2Master.write(my_buffer,my_buffer_len);  

I then go into a while loop checking the transmit complete flag

if((USART2->SR & USART_SR_TC)){

I'm using a slow baud rate (19.2k).

I don't fully understand how a multi-byte write occurs.  Does a multi-byte write rely on an interrupt to send each byte of the multi-byte data to the USART?  Or does the USART hardware contain it's own buffer, and automatically (without support from software) sequence the bytes to the USART transmit data register.

If software is required, then I'm guessing the only way to avoid the possibility of these gaps is to implement serial xmit using DMA .  But even if software is required, it still doesn't explain why the Transmit Complete flag is true in the middle of a transmission.

Any ideas?

Randy

[Tesla DeLorean]

Not clear on your implementation of write()

If you spin on TXE and stuff the USART->DR there really shouldn't be any inter-symbol gaps, beyond the stop bit(s), watch for other interrupts/callbacks or code that can block.

DMA and IRQ should be solid here.

Don't look at the USART registers in a Debugger Register View, as this has secondary effects via reads of DR and SR