what's the __COMPILER_BARRIER?

[Matt.Dash]

hi, everyone!

May you have a nice day!

In en.stm32cubeg4_v1-5-0\STM32Cube_FW_G4_V1.5.0\Projects, core_cm4.h file.

I encounter the following codes:

__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)

{

  if ((int32_t)(IRQn) >= 0)

  {

    __COMPILER_BARRIER();

    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));

    __COMPILER_BARRIER();

  }

}

So the questions are:

1. what's the meaning of __COMPILER_BARRIER();?
2. why it's called here, is ISERx registers related to it?
3. could anyone share some literature on this?

thank you for your attention!

Best wishes!

[Tesla DeLorean]

Goto the definition of the function

T​ypically such things are designed to stop the compiler moving or optimizing code that has primary, or secondary, behavior the compiler can't understand.

O​r involves a memory fencing requirement, where data needs to reach its final destination before completion. So pipeline and write buffers must complete before next instruction starts.

[Matt.Dash]

hi tesla, thank you for your answer~

here is its definition:

#define __COMPILER_BARRIER() __ASM volatile("":::"memory")

it seems conform to the following format:

asm(code : output operand list : input operand list : clobber list);

I am new to this, where should I go to find related literature  or pdf ?

thank you very much!

[Matt.Dash · Accepted solution]

HI, everyone.

I think this post answers my question in detail, lets close this topic.

gcc - difference in mfence and asm volatile ("" : : : "memory") - Stack Overflow

[Tesla DeLorean]

The predominant hazard with the NVIC and peripherals is that the write-buffers clearing the source of an interrupt can be slower than the interrupt tail-chaining mechanics resulting in it wanting to re-enter the IRQHandler somewhat spuriously.  When you double-check the source it will have been cleared. So robust coding of the Handler is recommended.