Thanks for the reply. I also noticed the processor is included in the document, but only as far as section 38 where the bootloader flow is described well enough. However, this processor is conspicuously absent from section 60 of the document where timing numbers are discussed. I considered using timing numbers from the 74XXX/75XXX which is in that section as well as the 72XXX/73XXX family, but there are differences that impact not only the startup timing but the flow timing thereafter. What we need added to section 60 is the timing specific to the 76XXX family. Further although I don't use the CAN peripheral it is in the boot loader connection sensing loop and cannot possibly take 0ms to complete, it appears that the CAN peripheral sensing timing is missing from this section as well! I don't know what the overall loop takes to complete for this processor without this information.
Since we use the serial connection, that is my focus but the flowchart suggests that the processor isn't always on task for sensing the baud rate. Perhaps the diagram is misleading and the whole thing is interrupt based? If so they should put some sort of perimeter bubble around all of the peripheral detection blocks to indicate they are happening continuously, or at least indicate as much in a note of some sort. I would hope that this is indeed an interrupt based scheme such that after I wait for the boot loader startup time (whatever that may be for this processor) that the 0x7f byte can be sent by the host at any time thereafter and that the serial bootloader portion would then take over as is described in the document. Again, this is not clear.
