2016-07-28 07:22 PM
I have the 32F746G DISCOVERY. I am using IAR tools.
I�m using that PCB to adapt my STM32F4xxx RTOS to the Cortex-M7 product line. I had a bit of trouble putting my ROM image at 0x0800000 and my RAM starting at 0x20000000 but a few mods to the .icf (linker helper file) fixed that.Then there was that �DTCM data RAM clock enable� bit in RCC_AHB1ENR. It�s set by default but my tendency to assume (sometimes incorrectly) that bits I don�t care about are zero. Setting that bit ended some serious confusion. And now the RTOS seems to work just fine but only when my idle loop does not include a Wait For Interrupt instruction.<code>IdleTask; wfi ;with this line enabled I get random jumps to location zero; and other badness requiring a reset b IdleTask</code>The wfi worked in my Cortex-M4 RTOS version as well as in my Cortex-M0 version. I would love to be able to use it my Cortex-M7 RTOS.Ideas, anybody? = = = = =FWIW, using the following code FIRST THING AFTER RESET made serious fault recovery almost easy. (Code is for the 32F746G DISCOVERY board.) You will likely need to recast these seven instructions for use in your environment.<code> ldr r0,=baseRCC ldr r1,=((1<<20)+(1<<('I'-'A'))); bit 20 is �DTCM data RAM clock enable� str r1,[r0,&sharpRCC_AHB1ENR] ldr r0,=baseGPIOI; PORTI bit 11 set = pressed (PCB has pull down resistor)waitWhilePressed ldr r1,[r0,&sharpGPIO_IDR] lsls r1,r1,&sharp31-11 ;i.e. bit 11 to sign bit bmi waitWhilePressed ;loop 'till key released</code>When some nasty state prevents your IDE from loading new code have the above code already loaded. Press and hold the blue user switch, tap the black reset switch, start code loading then release the blue switch.This leaves PORTI enabled. Reset the PORTI bit in RCC_AHB1ENR if desired.<b>I want ideas about that wfi instruction.</b> I have likely left something out. #rtos #wfi #32f746g-discovery2016-07-29 01:04 AM
> The wfi worked in my Cortex-M4 RTOS version as well as in my Cortex-M0 version. I would love to be able to use it my Cortex-M7 RTOS.
A quick guess - the major architectural difference of the M7, compared to M0..M4 is the presence of cache (instruction and data). Perhaps disabling them helps.