Hello,
I am currently using the STM32N657-DK board with X-CUBE-AI (ST Edge AI Core v2.2.0).
I have successfully converted a TensorFlow Lite model to run on the NPU and can build and flash the firmware without issues.
Problem
When I call the function
ret = LL_ATON_RT_RunEpochBlock(&NN_Instance_Default);
it never returns.
The variable ret never reaches LL_ATON_RT_DONE, and it seems that the NPU interrupt (NPU3_IRQn) is not triggered.
Current configuration
Clock and Reset
Enabled the NPU clock and released the reset:
__HAL_RCC_NPU_CLK_ENABLE(); __HAL_RCC_NPU_FORCE_RESET(); __HAL_RCC_NPU_RELEASE_RESET();In set_clk_sleep_mode(), the NPU sleep-mode clock is also enabled.
Interrupt routing
In the Secure project:
NVIC_DisableIRQ(NPU3_IRQn);NVIC_ClearPendingIRQ(NPU3_IRQn);NVIC_SetTargetState(NPU3_IRQn); // route to NonSecureIn the NonSecure project:
HAL_NVIC_SetPriority(NPU3_IRQn, 0, 0);HAL_NVIC_EnableIRQ(NPU3_IRQn);void NPU3_IRQHandler(void){printf(">> NPU IRQ triggered\r\n");ATON_STD_IRQHandler();}
RIF / RISAF configuration
Configured NPU master/slave attributes to NonSecure + privileged.
Added RISAF regions so that NonSecure code can access NPU RAM3–RAM6 (0x3420_0000–0x343C_0000):
RISAF_ConfigRegion(3, 0x34200000, 0x70000, RISAF_ATTR_NONSECURE | RISAF_ATTR_PRIV); RISAF_ConfigRegion(4, 0x34270000, 0x70000, RISAF_ATTR_NONSECURE | RISAF_ATTR_PRIV); RISAF_ConfigRegion(5, 0x342E0000, 0x70000, RISAF_ATTR_NONSECURE | RISAF_ATTR_PRIV); RISAF_ConfigRegion(6, 0x34350000, 0x70000, RISAF_ATTR_NONSECURE | RISAF_ATTR_PRIV);
Activation buffer
Declared in the .noncacheable section with 32-byte alignment.
Questions
Is any additional RISAF or RIF configuration required to allow the NPU to generate interrupts in a NonSecure environment?
To enable Epoch Controller interrupts, do I need to explicitly configure ATON_INTCTRL registers (e.g. ATON_INTCTRL_CTRL_SET_EN, ATON_INTCTRL_INTORMSK0_SET), or should X-CUBE-AI handle this automatically?
Could this issue be related to the memory attributes of the NPU region (cacheable vs. non-cacheable)? If so, what configuration is recommended?
Are there any known issues with NPU interrupt routing (NPU3_IRQn) in Secure/NonSecure TrustZone projects on STM32N6?
Thank you very much for your support.
I am attaching all the files I have modified so far.
