STM32N6 getting stuck in USB_CoreReset( )

[johndoeEngg]

I urgently need to get USB High Speed working on USB1 of the STM32N6570-DK. I have attached the .ioc file I am using.

I am able to get the GPIO_IOToggle project working on the board. I am able to put breakpoints step through the code.

I am using  STM32CubeIDE version 1.18.0 (Build: 24413_20250227_1633 (UTC)).

As a second step, I need ThreadX working on the board.

[FBL]

Hi @johndoeEngg 

The issue occurs when the function releases a timeout while waiting for the USB Core Soft Reset to finish. This timeout happens when the bit CSRST is set in the OTG_GRSTCTL register.

The root cause could be related to the PHY not being properly initialized. After enabling PHY's clock, the sequence should be followed by a delay of 10 cycles before writing core soft reset. This delay is necessary to ensure proper synchronization before resetting USB controller.

    /** Initializes the peripherals clock */
    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
    PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;

    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
    {
      /* Initialization Error */
      Error_Handler();
    }

    /** Set USB OTG HS PHY1 Reference Clock Source */
    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1;
    PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;

    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
    {
      /* Initialization Error */
      Error_Handler();
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();

    LL_AHB5_GRP1_ForceReset(0x00800000);
    __HAL_RCC_USB1_OTG_HS_FORCE_RESET();
    __HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET();

    LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
    LL_AHB5_GRP1_ReleaseReset(0x00800000);

    /* Peripheral clock enable */
    __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();

    /* Required few clock cycles before accessing USB PHY Controller Registers */
    HAL_Delay(1);

    USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4);
    /*Set the PHY reference clock speed to 24 MHz */
    USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
                                (0x2 << 4)  |
                                (0x1 << 2)  |
                                 0x1U;

    __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET();

    /* Required few clock cycles before Releasing Reset */
    HAL_Delay(1);

    __HAL_RCC_USB1_OTG_HS_RELEASE_RESET();

    /* Peripheral PHY clock enable */
    __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();

HAL_Delay(1) introduced here is dependent on CPU frequency and not reliable. You can insert __NOP() to ensure that the delay is consistent. The volatile keyword ensures that the loop is not optimized away by the compiler.

 /* Required few clock cycles before accessing USB PHY Controller Registers */
        for (volatile uint32_t i = 0; i < 10; i++) {
            __NOP(); // No Operation instruction to create a delay
        }