STM32H7RS USB USB_OTG_HS PCD_SPEED_FULL as CDC Device: Enumeration Fails, Trace shows Stalls

[h p]

Hello,

On a STM32H7RS are using the USB_OTG_HS peripheral in PCD_SPEED_FULL mode using internal clock.

After I was able to configure the clock so that the MCU is responding on enumeration requests. The responses however seem to be partially incorrect; the trace tool shows stalls.

I did not found an example in current https://github.com/STMicroelectronics/STM32CubeH7RS

The following changes are applied to a CubeMX generated project

main.c SystemClock_Config:

LL3.PLLN was set to output 24 MHz

RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL3.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL3.PLLM = 4;
RCC_OscInitStruct.PLL3.PLLN = 60;
RCC_OscInitStruct.PLL3.PLLP = 2;
RCC_OscInitStruct.PLL3.PLLQ = 40;
RCC_OscInitStruct.PLL3.PLLR = 16;
RCC_OscInitStruct.PLL3.PLLS = 2;
RCC_OscInitStruct.PLL3.PLLT = 2;

Configure CRS

  __HAL_RCC_CRS_CLK_ENABLE();

  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; // default
  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB_OTG_HS; //RCC_CRS_SYNC_SOURCE_USB_OTG_FS;
  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000); // RCC_CRS_RELOADVALUE_DEFAULT = 0x0000BB7FU
  RCC_CRSInitStruct.ErrorLimitValue = 34; // = RCC_CRS_ERRORLIMIT_DEFAULT
  RCC_CRSInitStruct.HSI48CalibrationValue = 32; // = RCC_CRS_HSI48CALIBRATION_DEFAULT

  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);

usbd_conf.c

void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
  if(pcdHandle->Instance==USB_OTG_HS)
  {
  /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */

  /* USER CODE END USB_OTG_FS_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHYC;
    PeriphClkInit.UsbPhycClockSelection = RCC_USBPHYCCLKSOURCE_PLL3Q;
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
    {
      Error_Handler();
    }


  /** Enable USB Voltage detector
  */
    if(HAL_PWREx_EnableUSBVoltageDetector() != HAL_OK)
      Error_Handler();
    HAL_PWREx_EnableUSBHSregulator();

    /* Peripheral clock enable */
    __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
    __HAL_RCC_USBPHYC_CLK_ENABLE();

    /* Peripheral interrupt init */
    HAL_NVIC_SetPriority(OTG_HS_IRQn, 5, 0);
    HAL_NVIC_EnableIRQ(OTG_HS_IRQn);
  /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */

  /* USER CODE END USB_OTG_FS_MspInit 1 */
    }
}

I checked the following related posts

https://community.st.com/t5/stm32-mcus/faq-troubleshooting-a-usb-core-soft-reset-stuck-on-an-stm32/ta-p/803224

https://community.st.com/t5/stm32-mcus-embedded-software/stm32h7rs-usb-hs-failure-device-descriptor-request-failed/m-p/729048/

STM32H7R3 USB FS device enumeration problem | Community

What is missing/wrong in my configuration?
Many thanks for any help.

[FBL]

Hello @h p 

Would you attach your example code to reproduce on my end?

[h p]

Hello @FBL 

I created a CubeMX Project and applied necessary patches (MOD_1, MOD2, optionally MOD_3 switches in stm32h7rsxx_hal_conf). It works on the STM32H7S78-DK. The enumeration works successfully. The SYSCLK is 64MHz (MOD_4 set to 0).

When the SYSCLK is switched to 600 MHz using PLLCLK (MOD_4 set to 600) I observe the same problem as on our board: The enumeration fails. Either the trace shows incomplete frames or no activity at all.

The attached project demonstrates the problem. If MOD_4 is set back to 0 then the enumeration is successful.

Best reards,

@h p 

[FBL]

Hi @h p 

Based on your code provided,

#if MOD_4 == 600
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI;

HSI48 should not be part of the SYSCLK source setup.
On STM32H7RS, HSI48 is intended as a kernel clock for specific peripherals such as USB and RNG, as described in the reference manual and the CubeMX clock tree. It is not meant to feed the main system clock.

Second, you should use better dividers like  

RCC_OscInitStruct.PLL1.PLLM = 8; //instead of 32 
RCC_OscInitStruct.PLL1.PLLN = 75; //instead of 300

This would be more consistent with generating a 600 MHz system clock, depending on your input clock source and the rest of the PLL configuration.

 Also here, I assume this should be inversed 

#if MOD_4 != 0
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
#else
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
#endif