Hi,
For USB HS device mode DMA to work correctly, we need to consider:
1- address alignment (4byte align due to hardware design) ... OTG_D(I/O)DMAx registers
2- size of data (not recommended but can be set in byte size using HBSTLEN in OTG_GAHBCFG register)
3- location of buffer in memory(be accessable for usb dma due to hardware design)
stm32f7 USB HS DMA needs the addresses to be 4byte aligned
*** One side is the buffer in memory which can be set to be 4byte aligned using gcc __attribute__(__aligned__(4)) directive
*** Another side is the usb Rx fifo (regarding OUT endpoints) whose address can be NOT 4byte aligned, due to reception of previous packet not multiple of 4bytes
Question1: are the Rx fifo addresses needs to be 4byte aligned for dma to work correctly? I mean, Host must send only usb packets in size of mutilpe 4bytes so that alignment does not disorder?
Queation2: If 4byte alignment is a requirement for dma for fetching data from usb Rx fifo to memory, then a packet residing on NOT a 4byte aligned address in fifo can cause ALL OUT endpoints to stuck as the Rx fifo is shared among all endpoints. Is that right?
Question3: how is usb fifo arrangement? I read some parts are used for status, nack, dma register. Could you please give some information or document mentioning the internal arrangement of usb fifo?
Thanks in advance for your help
