STM32F417IG single ended external clock bypass

[santosh239955]

Posted on October 26, 2014 at 20:01

Hi,

I am looking for some info regarding the external clock bypass conditions for STM32F417IG. There was not sufficient info in the datasheet. But, in the reference manual I could find some related data regarding how it can be done. Another problem was the Clock Config tool does not support the external clock bypass conditions. So, that was a problem in generating the required related C code to dump. I just wanted to confirm if the following changes in the system_stm32f4xx.h header file would be sufficient to use the chip in bypass conditions by feeding it using an external single ended clock source and have it communicating with the computer with VCP: I set it to pll_source_hse_bypass. and  RCC->CR |= ((uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP));   RCC->CR |= ((uint32_t)RCC_CR_HSEON); In the main.c: I have the following config- &sharpdefine HSE_VALUE((uint 32_t)8000000) should I leave it as it is or make any changes to this in main? I request you to please provide any other samples/code/reference design if available about the same conditions. I already tried with the modifications mentioned above and I think I partially bricked one of the device. I am able to program the flash but it is not able to communicate with pc as the VCP is not being detected. I thereby request you to please look into this and provide some solutuon. Thanks, Sa #stm32f417 #stm32f417 #stm32f417 #hse-hsi-pll-rcc #vcp-stm32f4 #rtfm #external-clock #hse-config

[Tesla DeLorean]

Posted on October 30, 2014 at 04:13

Clocking from HSI, attached

________________ Attachments : core417i_hsi_vcp.hex : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HzMt&d=%2Fa%2F0X0000000bLP%2F21F2ovXB86JR2Ip.1mjmF_zxymhnfJDzVC4oyT6wT8Y&asPdf=false

[santosh239955]

Posted on October 30, 2014 at 04:21

Does clocking from hsi mean a normal application binary?

which works on internal clock?

[Tesla DeLorean]

Posted on October 30, 2014 at 04:50

Does clocking from hsi mean a normal application binary? which works on internal clock?

I'm not sure what meaning you're trying elicit here. It uses the HSI as a clock source, and uses that to drive the PLL. I wouldn't use it for a production USB solution, over voltage and temperature, but should be sufficient for demonstrational purposes.

[santosh239955]

Posted on October 31, 2014 at 17:39

Clive,

Is there anyway to check if the external clock which is being given can be measured to see if it being accepted?

[Tesla DeLorean]

Posted on October 31, 2014 at 18:24

''If you wish to confirm the internal clocks they can be routed out MCO1 (PA8)''

This includes what's being pulled in externally (internal copies there of). Depending on the part/clock TIM9 and TIM12 (check Ref Manual) provides a means of benchmarking one clock against another. ie ticks of a fast clock against a 32.768 KHz oscillator..

[santosh239955]

Posted on November 04, 2014 at 18:46

hi clive,

can you please send the project/code of the example 50mhz vcp you attached?

[Tesla DeLorean]

Posted on November 05, 2014 at 06:32

This is the quick mash-up that I created for the 50 MHz external source

https://drive.google.com/file/d/0B7OY5pub_GfINE1aNnJONXhEcmc/view?usp=sharing

[Tesla DeLorean]

Posted on November 05, 2014 at 17:14

I will drop the clock freq to 192 which is a multiple of 48. Could you please tell if these settings would need any other software changes?

Huh?

[santosh239955]

Posted on November 06, 2014 at 18:15

Thanks fr the mashup.

[santosh239955]

Posted on November 06, 2014 at 18:40 hi kumar

the maximum HSE bypass frequency is 50 MHz (maximum HSE oscillator frequency is 26 MHz).

However, there is no way to direct a 48 MHz bypass signal directly to the USB peripheral, so the PLL must be used.

The input to the PLL clock can be HSE bypass / PLL_M, which must be between 1 and 2 MHz.

So, if you are using a 26 MHz signal, you could use:

PLL_M = 13, which will give 26 MHz / 13 = 2 MHz as the PLL input clock

PLL_N = 192, which will give 2 MHz x 192 = 384 MHz as the main PLL clock

PLL_Q = 8, which will give 384 MHz / 8 = 48 MHz as the USB clock.

PLL_P should be a value to get your system clock to its desired frequency, which can be up to 168 MHz.

Alternatively, to get the maximum possible frequencies, you can set:

PLL_M = 13, which will give 26 MHz / 13 = 2 MHz as the PLL input clock

PLL_N = 336, which will give 2 MHz x 336 = 672 MHz as the main PLL clock

PLL_Q = 14, which will give 672 MHz / 14 = 48 MHz as the USB clock.

PLL_P should be a value to get your system clock to its desired frequency, which can be up to 168 MHz (minimum value for PLL_P would be 4, in this case).

Using a 50 MHz bypass signal:

PLL_M = 25, which will give 50 MHz / 25 = 2 MHz as the PLL input clock

PLL_N = 336, which will give 2 MHz x 336 = 672 MHz as the main PLL clock

PLL_Q = 14, which will give 672 MHz / 14 = 48 MHz as the USB clock.

PLL_P should be a value to get your system clock to its desired frequency, which can be up to 168 MHz (minimum value for PLL_P would be 4, in this case).