STM32F417IG single ended external clock bypass

[santosh239955]

Posted on October 26, 2014 at 20:01

Hi,

I am looking for some info regarding the external clock bypass conditions for STM32F417IG. There was not sufficient info in the datasheet. But, in the reference manual I could find some related data regarding how it can be done. Another problem was the Clock Config tool does not support the external clock bypass conditions. So, that was a problem in generating the required related C code to dump. I just wanted to confirm if the following changes in the system_stm32f4xx.h header file would be sufficient to use the chip in bypass conditions by feeding it using an external single ended clock source and have it communicating with the computer with VCP: I set it to pll_source_hse_bypass. and  RCC->CR |= ((uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP));   RCC->CR |= ((uint32_t)RCC_CR_HSEON); In the main.c: I have the following config- &sharpdefine HSE_VALUE((uint 32_t)8000000) should I leave it as it is or make any changes to this in main? I request you to please provide any other samples/code/reference design if available about the same conditions. I already tried with the modifications mentioned above and I think I partially bricked one of the device. I am able to program the flash but it is not able to communicate with pc as the VCP is not being detected. I thereby request you to please look into this and provide some solutuon. Thanks, Sa #stm32f417 #stm32f417 #stm32f417 #hse-hsi-pll-rcc #vcp-stm32f4 #rtfm #external-clock #hse-config

[santosh239955]

Posted on October 27, 2014 at 21:33

Thanks for the explanation. I will limit the hse to <50 mhz.

Also, an update(just found out): The workaround for using clock config tool in hse bypass conditions is to set the HSE_VALUE to the HSE bypass oscillator's frequency.

[Tesla DeLorean]

Posted on October 27, 2014 at 21:49

I'm not sure if the PLL is the limiting factor here or not, you'd have to find someone who understood the critical paths in the design. ST indicate 50 MHz is where it was designed to work, but not tested in production. I'd assume the 50 MHz number relates to Ethernet PHY clocking sources.

The PLL's VCO wants to dwell in the 192 to 432 MHz range, they want the PLL comparison frequency at 1 to 2 MHz, and the M Divider has 6-bits with suggested range of 2-63. If that divider/counter works at high speeds, one might be able to push 126 MHz. The N Divider is bigger and capable of 432 MHz operation. One could presumably experiment with the corners of this design over frequency, voltage and temperature. I don't know of anyone who's does such a characterization. For generating other frequencies, there is the I2SPLL with output via MCO2

[Tesla DeLorean]

Posted on October 27, 2014 at 21:54

I'll note that you can run the CPU directly from HSE, and still run the PLL to generate the 48MHz for SDIO, USB, etc.

[santosh239955]

Posted on October 27, 2014 at 22:23

When you say the M-divider can be modified to push to 126 Mhz. All this is internal, right? We cannot send in a higher freq than 50 and increase this 126 to even higher value.

50 MHz is for single ended sources and 26 MHz for external crystals. I think PLL is the critical block here because. If the pll is bypassed then the external clock can control the chip and peripherals(if they can handle high frequencies).

[Tesla DeLorean]

Posted on October 28, 2014 at 00:40

The node you're trying to clock for the CPU and peripheral divisors (APB1/APB2) is rated to 168 MHz.

What I'm suggesting is that the PLL gearing *MIGHT* be able to get to 126 MHz, as 126 MHz DIV 63 = 2 MHz which is the top end of the comparison frequency range for the PLL, with the maximal divisor.

[santosh239955]

Posted on October 30, 2014 at 00:14

Clive,

For HSE bypass clock of 50 MHz these are the changes made-

//In the PLL parameters

#define PLL_M      25      

#define PLL_N      336        #define PLL_P      168       #define PLL_Q      14  

//In the SetSysClock fn

RCC->CR |= (uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP);    In main.c #

define

HSE_VALUE((uint 32_t)50000000) But, the USB is not being recognized when I plug the 50 Mhz clock and power it up. Do you think any change required? Thanks

[Tesla DeLorean]

Posted on October 30, 2014 at 00:37

#define PLL_M      50      

#define PLL_N      336        #define PLL_P      2       #define PLL_Q      7

[santosh239955]

Posted on October 30, 2014 at 01:37

Clive,

No change even with the parameters you mentioned. I also tried lowering the frequency from 50 Mhz but still same case

[Tesla DeLorean]

Posted on October 30, 2014 at 03:37

Perhaps the problem is some place else?

Attached is a VCP example that should work at 50 MHz ________________ Attachments : core417i_50mhz_vcp.hex : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HzP7&d=%2Fa%2F0X0000000bLO%2FUhcXjQKVEYqo7Unj.e2B97sBirv5i8LR3wsF0vVUu_w&asPdf=false

[santosh239955]

Posted on October 30, 2014 at 03:50

Clive,

Thanks for the file I flashed the hex file you provided. and gave a 50mhz clock on ph0 pin. It still does not enumerate It is only able to enumerate in normal clock condition