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STM32 Discovery kit Microphone data reading using DFDSM peripheral (Doubts and problems)

danieldeiana
Associate

Hi all, i decided to write a simple program on my stm32 board (B-L475E-IOT01A), here are some of the setting of my peripheral: 

i read input data from channel 2 sampling data on rising edge

fft1.png

 

 

 

The clock frequency at which the microphone is outputting PDM bits is 80 Mhz (by clock tree) divided by 40 using the internal prescaler

fft2.png

for the filtering on pdm signal i choose (by using the table) sinc3 with FOSR = 32, so that my output data is represented on a 16 bit signed integer.

fft3.png

the dma mode is circular and i use one bufffer for dma and the other buffer for pcm samples, the samples are mono so the audio buffer contains only one channel samples

here is a snippet of my code, i didnt include half buffer and full buffer callbacks, they just update the associated flags.

 

fft4.png

 

The problem with this program is that, the audio buf data is always negative (which i suppose is wrong because we are talking about some pcm waveform). What am i doing wrong?

1 REPLY 1
Dor_RH
ST Employee

Hello @danieldeiana,

There are several potential issues that might cause incorrect data in the audio buffer. To address these, you should refer to the STM32L4 Reference Manual, which provides detailed information about the DFSDM peripheral and its configuration.

Also, you should:

  • Ensure that the PDM to PCM conversion is correctly implemented. The SINC3 filter with FOSR = 32 should be correctly configured to output 16-bit signed integers.
  • Verify that the DMA is correctly configured to handle the data transfer. Ensure that the buffer sizes and addresses are correctly set up.
  • Make sure that the buffer handling logic is correctly implemented. If the half buffer and full buffer callbacks are not correctly updating the flags or processing the data, it could lead to incorrect data being stored in the audio buffer.
  • Ensure that the microphone is correctly configured and that the clock settings are accurate. The PDM clock should be correctly divided, and the sampling should be done on the rising edge as specified.

I hope my answer has helped you. When your question is answered, please select this topic as solution that answered you, it will help others find that answer faster.

Thanks for your contribution.

Dor_RH