2024-01-22 01:14 AM
Hello,
i have a question regarding the RM0444. On page 74 chapter 3.3.6, is mentioned the following:
"During a program/erase operation to the Flash memory, any attempt to read the Flash
memory stalls the bus. The read operation proceeds correctly once the program/erase
operation has completed."
Does that mean the system bus is stalled or just the Flash memory interface?
For example what happens if i have an interrupt, which is running from RAM, while the bus/Flash memory interface has been stalled because a Flash read operation has been executed while a Flash write operation is ongoing?
Will the interrupt be handled whilst the Flash write operation is ongoing?
Thanks in advance!
Best regards
Chris
Solved! Go to Solution.
2024-01-22 06:30 AM - edited 2024-01-22 06:31 AM
Maybe "stall" is not the best word in this context.
After FLASH programming/erasing has been started, upon the first attempt to read from FLASH (either code fetch or data read) from processor, FLASH returns a WAIT signal which makes the processor unable to continue, this signal lasts until programming ends.
In other words, if you want some code running during FLASH programming, it must be entirely located in RAM (including the code which started the programming, and should be interrupts involved, including the interrupt vector table).
JW
2024-01-22 06:30 AM - edited 2024-01-22 06:31 AM
Maybe "stall" is not the best word in this context.
After FLASH programming/erasing has been started, upon the first attempt to read from FLASH (either code fetch or data read) from processor, FLASH returns a WAIT signal which makes the processor unable to continue, this signal lasts until programming ends.
In other words, if you want some code running during FLASH programming, it must be entirely located in RAM (including the code which started the programming, and should be interrupts involved, including the interrupt vector table).
JW
2024-01-22 10:29 PM
Thank you very much, that fits with what I observed.