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Problem with TX CLK for MII interface (analog switch between PC3_C and PC3)

EngyCZ
Associate II

Hi.

I have a problem with MII PHY interface STE100P connected to STM32H743ZIT6 (package LQFP144). Communication works only on 10Mbps. On 100Mbps works only packet receiving. Transmitting is not working at all. I spend several weeks to find why. And now I finally know why.

When the PHY is connected to 100Mbps network, TX state machine stops processing TX descriptors (OWN bit stuck on 1 - DMA owns the descriptor). Also "Flush Transmit Queue" never ends.

Problem is with the TX_CLK signal connected to PC3_C pin on LQFP144 package variant. With 10Mbps speed the clock signal is 2.5MHz. With 100Mbps the clock signal is 25Mhz.

ETH_MII_TX_CLK signal is connected to PC3 and through the analog switch, it is connected to PC3_C. The analog switch can be closed by setting 0 to PC3SO in SYSCFG_PMCR register. The problem is in this analog switch itself because it doesn't have enough throughput for 25MHz signal clock and TX state machine lost the clock and stops working. It works only witch signal amplitude increased to 4V on PC3_C pin. With 3.3V it doesn't work because of high attenuation of an analog switch with 25Mhz signal.

RX clock is working because it can be connected directly to PA1 without an analog switch. PC3 pad is available only on TFBGA240+25 package.

This should be somehow fixed or noticed in the documentation or errata sheet.

Analog switch 0690X0000089Dk7QAE.png

Working with increased voltage to 4V peek-peek

0690X0000089DgFQAU.bmp

Not working with 3V peek-peek

0690X0000089DgPQAU.bmp

Not working with voltage +shift

0690X0000089DgUQAU.bmp

Not working with voltage -shift

0690X0000089DgZQAU.bmp

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